PIC18F6620 Microchip, PIC18F6620 Datasheet - Page 343

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PIC18F6620

Manufacturer Part Number
PIC18F6620
Description
Microcontroller
Manufacturer
Microchip
Datasheet

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TABLE 26-26: A/D CONVERSION REQUIREMENTS
 2004 Microchip Technology Inc.
130
131
132
135
136
Note 1:
Param
No.
2:
3:
4:
5:
T
T
T
T
T
Symbol
AD
CNV
ACQ
SWC
AMP
ADRES register may be read on the following T
See Section 19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when
input voltage has changed more than 1 LSb.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
is 50 .
On the next Q4 cycle of the device clock.
The time of the A/D clock period is dependent on the device frequency and the T
PIC18F6520/8520/6620/8620/6720/8720
A/D Clock Period
Conversion Time
(not including acquisition time) (Note 1)
Acquisition Time (Note 3)
Switching Time from Convert
Amplifier Settling Time (Note 2)
Characteristic
DD
to AV
PIC18FXX20
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
SS
, or AV
Sample
SS
to AV
CY
DD
cycle.
Min
). The source impedance (R
1.6
3.0
2.0
3.0
15
10
11
1
(Note 4)
20
20
Max
6.0
9.0
12
(5)
(5)
Units
T
AD
s
s
s
s
s
s
s
T
T
A/D RC mode
A/D RC mode
-40 C
0 C
This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on C
OSC
OSC
AD
S
) on the input channels
based, V
based, V
clock divider.
Temp
Temp
Conditions
DS39609B-page 341
HOLD
+125 C
REF
REF
+125 C
).
full range
3.0V

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