74VCXH162244MTD Fairchild Semiconductor, 74VCXH162244MTD Datasheet

74VCXH162244MTD

Manufacturer Part Number

74VCXH162244MTD

Description

IC BUFF DVR 16BIT LOW V 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74VCXHr

Datasheet

1.74VCXH162244MTD.pdf (8 pages)

Specifications of 74VCXH162244MTD

Logic Type

Buffer/Line Driver, Non-Inverting

Number Of Elements

Number Of Bits Per Element

Current - Output High, Low

12mA, 12mA

Voltage - Supply

1.4 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Logic Family

VCX

Number Of Channels Per Chip

Polarity

Non-Inverting

Supply Voltage (max)

3.6 V

Supply Voltage (min)

1.4 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

High Level Output Current

- 12 mA

Low Level Output Current

12 mA

Minimum Operating Temperature

- 40 C

Number Of Lines (input / Output)

16 / 16

Output Type

3-State

Propagation Delay Time

7.6 ns at 1.8 V, 3.8 ns at 2.5 V, 3.3 ns at 3.3 V

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74VCXH162244MTD

74VCXH162244MTX

(Note 1)

74VCXH162244

Low Voltage 16-Bit Buffer/Line Driver with Bushold

and 26: Series Resistor in Outputs

General Description

The VCXH162244 contains sixteen non-inverting buffers

with 3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

The VCXH162244 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level

The 74VCXH162244 is also designed with 26

resistors in the outputs. This design reduces line noise in

applications such as memory address drivers, clock driv-

ers, and bus transceivers/transmitters.

The 74VCXH162244 is designed for low voltage (1.4V to

3.6V) V

The 74VCXH162244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Note 1: Use this Order Number to receive devices in Tape and Reel.

Logic Symbol

Order Number

applications with output capability up to 3.6V.

Package

Number

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TUBES]

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TAPE and REEL]

DS500231

series

Features

Pin Descriptions

1.4V to 3.6V V

3.6V tolerant control inputs and outputs

Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

–I

Pin Names

–O

3.3 ns max for 3.0V to 3.6V V

Human body model

Machine model

12 mA @ 3.0V V

series resistors in outputs

Package Description

Output Enable Input (Active LOW)

Bushold Inputs

Outputs

supply operation

)

200V

2000V

January 2000

Revised June 2005

Description

www.fairchildsemi.com

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74VCXH162244MTD Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Package Order Number Number 74VCXH162244MTD 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide MTD48 [TUBES] 74VCXH162244MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide ...

Page 2

Connection Diagram Functional Description The 74VCXH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( – Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. ...

Page 4

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current Control Pins I Data Pins I Bushold Input Minimum I(HOLD) Drive Hold Current I Bushold Input Over-Drive I(OD) Current to Change State I 3-STATE Output ...

Page 5

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t PLH t Output Enable Time PZL t PZH t Output Disable Time PLZ t PHZ t Output-to-Output Skew OSHL t (Note 9) OSLH Note 8: For add ...

Page 6

AC Loading and Waveforms (V TEST PLH PZL PZH FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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