T15N1M16A TM tech, T15N1M16A Datasheet - Page 7
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T15N1M16A
Manufacturer Part Number
T15N1M16A
Description
64K X 16 LOW POWER CMOS STATIC RAM
Manufacturer
TM tech
Datasheet
1.T15N1M16A.pdf
(13 pages)
(Address Controlled,
TIMING WAVEFORMS
READ CYCLE 1
READ CYCLE 2 (
(Chip Enable Controlled)
Notes (READ CYCLE) :
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
4. At any given temperature and voltage condition. t
5. Transition is measured 200mV from steady state voltage with load.
6. Device is continuously selected with CE =V
TM Technology Inc. reserves the right
to change products or specifications without notice.
V
and from device to device interconnection.
100% tested.
HZ
A d d r e s s
A d d r e s s
U B / L B
OH
and t
D O U T
D
or V
C E
OUT
O E
OHZ
OL
CH
TE
levels.
Previous Data Valid
are defined as the time at which the outputs achieve the open circuit condition referenced to
High-Z
CE
WE
=
t OH
=
V
OE
IH
)
t
LZ
=
t
t AA
BLZ
V , WE =
IL
t
OLZ
t
t
t
ACE
A A
BA
t
OE
IL
.
V
HZ
t RC
IH
P. 7
(max.) is less than t
, LB or/and
t
RC
Data Valid
UB
This parameter is sampled and not
=
LZ
V )
(min.) both for a given device
IL
t
Publication Date: JUL . 2002
OHZ
t
BHZ
t
HZ
t
OH
T15N1M16A
DON'T CARE
UNDEFINED
Revision: A