MT91L61 MITEL, MT91L61 Datasheet - Page 14

• Manufacturer Part Number: MT91L61
• Description: (MT91L60 / MT91L61) ISO2-CMOS 3 Volt Multi-Featured Codec
• Manufacturer: MITEL

MT91L60/61
Register Summary
14
Gain Control Register 1
Gain Control Register 2
RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB.
TxINC: When high, the transmit path nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.
RxFG
Receive Gain
Setting (dB)
n
(default) 0
= Receive Filter Gain bit n
Note: Bits marked "-" are reserved bits and should be written with logic "0"
RxINC RxFG
-1
-2
-3
-4
-5
-6
-7
-
7
7
STG
Side-tone Gain
n
(default) OFF
Setting (dB)
= Side-tone Gain bit n
-
6
6
-9.96
-6.64
-3.32
3.32
6.64
9.96
RxFG
2
0
0
0
0
0
1
1
1
1
RxFG
2
5
5
-
1
RxFG
RxFG
0
0
1
1
0
0
1
1
4
1
-
4
STG
0
0
0
0
1
1
1
1
0
RxFG
2
TxINC
0
1
0
1
0
1
0
1
3
3
-
0
STG
0
0
1
1
0
0
1
1
TxFG
STG
1
TxFG
2
2
2
2
Transmit Gain
n
Setting (dB)
= Transmit Filter Gain bit n
(default) 0
TxFG
STG
STG
0
1
0
1
0
1
0
1
1
1
1
2
3
4
5
6
7
0
1
1
TxFG
STG
ADDRESS = 00h WRITE/READ VERIFY
ADDRESS = 01h WRITE/READ VERIFY
0
0
0
0
TxFG
0
0
0
0
1
1
1
1
Advance Information
2
TxFG
Power Reset Value
Power Reset Value
0
0
1
1
0
0
1
1
XXXX X000
1000 0000
1
TxFG
0
1
0
1
0
1
0
1
0