MT91L61 MITEL, MT91L61 Datasheet - Page 16

• Manufacturer Part Number: MT91L61
• Description: (MT91L60 / MT91L61) ISO2-CMOS 3 Volt Multi-Featured Codec
• Manufacturer: MITEL

MT91L60/61
16
Control Register 2
CEn
DEn
D8
A/
Smag/ITU-T
CSL
1
1
1
0
0
0
0
CEn
2
7
low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel
register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation
and is ignored for SSI operation.
on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is
completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of
the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation.
When high, A-Law encoding/decoding is selected for the MT91L60/61. When low,
selected.
assignment is selected for the Codec input/output; true sign, inverted magnitude ( -Law) or true sign, alternate
digit inversion (A-Law).
When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When
When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0
When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default).
When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code
CSL
DEn
1
0
0
0
0
1
1
Note: Bits marked "-" are reserved bits and should be written with logic "0"
6
1
CSL
D8
1
0
1
0
1
0
1
5
0
A/
4
Bit Clock rate (kHz)
Smag/
ITU-T
1536
2048
4096
N/A
128
256
512
3
CSL
2
2
CSL
1
CLOCKin (kHz)
1
4096
4096
4096
1536
2048
4096
512
ADDRESS = 04h WRITE/READ VERIFY
CSL
0
0
Advance Information
SSI (default)
-Law encoding/decoding is
ST-BUS
Mode
Power Reset Value
SSI
SSI
SSI
SSI
SSI
0000 0010