ISL12024 Intersil Corporation, ISL12024 Datasheet - Page 12

• Manufacturer Part Number: ISL12024
• Description: Real-Time Clock/Calendar
• Manufacturer: Intersil Corporation

The effective on-chip series load capacitance, C
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C
controlled capacitors, C
and X2 pins to ground (see Figure 8). The value of C
C
The effective series load capacitance is the combination of
C
For example:
C
C
C
The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit, where:
DTR2 = 0 means frequency compensation is >0.
DTR2 = 1 means frequency compensation is <0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using three bits above.
C LOAD
C
C
X2
X1
LOAD
LOAD
LOAD
LOAD
X
DTR2
=
is given by the following formula:
and C
0
0
0
0
1
1
1
1
(
16 b5
(ATR = 00000) = 12.5pF,
(ATR = 100000) = 4.5pF, and
(ATR = 011111) = 20.25pF.
=
=
DTR REGISTER
⋅
⎛
⎝
---------------------------------- -
⎛
⎝
TABLE 5. DIGITAL TRIMMING REGISTERS
---------- -
C
16 b5
---------------------------------------------------------------------------------------------------------------------------- -
X2
1
X1
+
⋅
:
DTR1
8 b4
1
+
0
1
0
1
0
1
0
1
⋅
---------- -
C
+
1
8 b4
X2
LOAD
+
⋅
4 b3
⎞
⎠
⋅
+
X1
DTR0
4 b3
is changed via two digitally
+
⋅
0
0
1
1
0
0
1
1
and C
2 b2
⋅
12
+
2 b2
2
+
⋅
X2
1 b1
ESTIMATED FREQUENCY
⋅
, connected from the X1
+
1 b1
+
⋅
0.5 b0
+
⋅
0.5 b0
PPM
+10
+20
+30
-10
-20
-30
0
0
+
⋅
9
LOAD
)pF
+
9
⎞ pF
⎠
X1
,
(EQ. 2)
(EQ. 1)
and
ISL12024
PWR Register: SBIB, BSW
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in Battery Backup Mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in Battery
Backup Mode by setting this bit to “0” (default is “0”). See
“Power Control Operation” on page 13.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
options.
Option 1. Standard/Default Mode: Set “BSW = 0”
Option 2. Legacy Mode: Set “BSW = 1”
See “Power Control Operation” on page 13 for more details.
Also see “I
page 22 for important details.
Unique ID Registers
There are eight register bytes for storing the device ID.
(Address 0020h to 0027h). Each device contains these
bytes to provide a unique 64-bit ID programmed and tested
in the factory before shipment. These registers are read-
only, intended for serialization of end equipment, and cannot
be changed or overwritten.
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a non-volatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
much shorter cycle time (t = t
have no effect. The RWEL bit is reset by the completion of a
write to the CCR, so the sequence must be repeated to
again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an
incorrect number of bits or sending a start instead of a stop,
for example) the RWEL bit is not reset and the device
remains in an active mode. Writing all zeros to the status
1. Write a 02h to the Status Register to set the Write Enable
2. Write a 06h to the Status Register to set both the Register
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
2
C Communications During Battery Backup” on
DD
and Back Up Battery. There are two
BUF
). Writes to undefined areas
October 18, 2006
FN6370.1