ISL12024 Intersil Corporation, ISL12024 Datasheet - Page 18

• Manufacturer Part Number: ISL12024
• Description: Real-Time Clock/Calendar
• Manufacturer: Intersil Corporation

Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the 12ms (typ) write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the ISL12024 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12024 is
still busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12024 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. See the flow chart in
Figure 20. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the ISL12024 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the sixteen bit address is initialized to 00h. In this
way, a current address read immediately after the power-on
reset can download the entire contents of memory starting at
the first location. Upon receipt of the Slave Address Byte
with the R/W bit set to one, the ISL12024 issues an
acknowledge, then transmits eight data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. See Figure 19 for the address, acknowledge, and
data transfer sequence.
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
SDA BUS
A
R
S
T
T
18
1
ADDRESS
SLAVE
1
1
1
0
A
C
K
FIGURE 18. PAGE WRITE SEQUENCE
0 0 0 0 0 0 0
ADDRESS 1
WORD
ISL12024
A
C
K
ADDRESS 0
WORD
SIGNALS FROM
THE MASTER
SDA BUS
SIGNALS FROM
THE SLAVE
FIGURE 19. CURRENT ADDRESS READ SEQUENCE
FIGURE 20. ACKNOWLEDGE POLLING SEQUENCE
Issue Memory Array Slave
AFh (Read) or AEh (Write)
cycle complete. Continue
command sequence?
Byte load completed
Enter ACK Polling
Non-volatile write
Continue normal
A
C
K
by issuing STOP.
Read or Write
Address Byte
Issue START
PROCEED
returned?
command
sequence
ACK
1 ≤ n ≤ 16 for EEPROM array
1 ≤ n ≤ 8 for CCR
DATA
(1)
S
T
A
R
T
YES
YES
1
ADDRESS
SLAVE
1
1
1
NO
NO
1
DATA
A
C
K
(n)
Issue STOP
Issue STOP
DATA
A
C
K
October 18, 2006
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