ISL6405 Intersil Corporation, ISL6405 Datasheet
ISL6405
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ISL6405 Summary of contents
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... Voltage Regulator with I C Interface for Advanced Satellite Set-top Box Designs The ISL6405 is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise blocks (LNBs) of two antenna ports ...
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... ISL6405 ISL6405 (EPSOIC) TOP VIEW VSW2 1 COMP2 2 FB2 3 GATE2 4 PGND 2 5 CS2 6 ISL6405EEB SGND 7 BYPASS 8 PGND1 9 GATE1 10 CS1 11 FB1 12 COMP1 13 VSW1 14 ISL6405 (QFN) TOP VIEW PGND2 2 CS2 3 SGND 4 SEL18V1 ISL6405ER 5 SEL18V2 6 BYP 7 PGND1 8 GATE1 VCC 27 CPVOUT ...
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Block Diagram OLF1 OVERCURRENT COUNTER PROTECTION DCL LOGIC SCHEME 1 PWM OC1 LOGIC GATE1 10 Q CLK1 S PGND1 9 ILIM1 CS - AMP CS1 ∑ 11 SLOPE COMPENSATION COMP1 13 - FB1 12 VREF1 VSW1 14 VO1 20 ON ...
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... COMP1 COMP2 C12 12 3 FB1 FB2 14 1 VSW1 VSW2 20 22 VO1 VO2 DSQIN1 SCL 15 23 DSQIN2 SDA 26 16 ADDRESS CPSWIN 18 25 TCAP1 CPSWOUT 21 27 AGND CPVOUT C16 ISL6405EEB C9 + C14 C10 C11 Q2 C13 VO2 13V / 18V SCL C17 SDA C8 ...
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... Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time Linear Regulator Drop-out Voltage 5 ISL6405 Thermal Information Thermal Resistance (Typical, Note 1, 2) EPSOIC Package (Note 1, 2 QFN Package (Note 1, 2 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Storage Temperature Range . . . . . . . . . -40 Maximum Lead Temperature (Soldering 10s .300 (SOIC - Lead Tips Only) Operating Temperature range ...
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... These high current driver outputs are capable of driving the gate of a power FET. These outputs are actively held low when Vcc is below the UVLO threshold. VO1, 2 Output voltage of LNB A and LNB B respectively. 6 ISL6405 - +85 C, unless otherwise noted.Typical values are access to the system ...
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... Functional Description The ISL6405 dual output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for two low-noise blocks (LNBs) are available simultaneously in any output configuration. The device utilizes built-in DC/DC step-converters that, from a ...
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... Additionally, the QFN package offers two pins (SEL18V1, SEL18V2) for independent 13V/18V output voltage selection. When using these pins, the I initialized to 13V status. TABLE Bits SEL18V(1,2) 13V LOW 14V LOW xx HIGH xx HIGH 8 ISL6405 2 C bus bits should be O/P Voltage 13V 13V 18V 18V ...
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... SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6405 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW. SCL ...
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... TABLE 4. SYSTEM REGISTER 2 (SR2) R,W R,W ENT2 LLC2 Transmitted Data ( When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR1/SR2) of the ISL6405 via I microprocessor as shown below. The spare bits of SR1/SR2 can be used for other functions. VSEL1 EN1 OLF1 0 0 ...
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... I C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set the following Master generated clock bits, the ISL6405 issues a byte on the SDA data bus line (MSB transmitted first). DCL ISEL1/2 ...
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... D - 0.25(0.010 SIDE VIEW BOTTOM VIEW 12 ISL6405 M28.3B 28 LEAD WIDE BODY SMALL OUTLINE EXPOSED PAD 0.25(0.010 PLASTIC PACKAGE SYMBOL α C 0.10(0.004) P1 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 ISL6405 L32.5x5 C A ...