ISL6405 Intersil Corporation, ISL6405 Datasheet - Page 7

• Manufacturer Part Number: ISL6405
• Description: Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs
• Manufacturer: Intersil Corporation

Functional Description
The ISL6405 dual output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal
video recorder applications. Both supply and control
voltage outputs for two low-noise blocks (LNBs) are
available simultaneously in any output configuration. The
device utilizes built-in DC/DC step-converters that, from a
single supply source ranging from 8V to 14V, generate the
voltages that enable the linear post-regulators to work with
a minimum of dissipated power. An undervoltage lockout
circuit disables the circuit when VCC drops below a fixed
threshold (7.5V typ).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone
of 22kHz in accordance with DiSEqC (EUTELSAT)
standards. No further adjustment is required. The 22kHz
oscillator can be controlled either by the I
(ENT1/2 bit) or by a dedicated pin (DSQIN1/2) that allows
immediate DiSEqC data encoding separately for each LNB.
(Please see Note 1 at the end of this section.) All the
functions of this IC are controlled via the I
to the system registers (SR1, SR2). The same registers
can be read back, and two bits will report the diagnostic
status. The internal oscillator operates the converters at ten
times the tone frequency. The device offers full I
compatible functionality, 3.3V or 5V, and up to 400kHz
operation.
If the Tone Enable (ENT1/2) bit is set LOW through I
the DSQIN1/2 terminal activates the internal tone signal,
modulating the dc output with a 0.3V, 22kHz, symmetrical
waveform. The presence of this signal usually gives the LNB
information about the band to be received.
Burst coding of the 22kHz tone can be accomplished due to
the fast response of the DSQIN1/2 input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
When the ENT1/2 bit is set HIGH, a continuous 22kHz tone
is generated regardless of the DSQIN1/2 pin logic status for
the corresponding regulator channel (LNB-A or LNB-B). The
ENT1/2 bit must be set LOW when the DSQIN1 and/or
DSQIN2 pin is used for DiSEqC encoding.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.25µf. In order to minimize the power dissipation,
the output voltage of the internal step-up converter is
adjusted to allow the linear regulator to work at minimum
dropout.
When the device is put in the shutdown mode (EN1,
EN2 = LOW), both PWM power blocks are disabled. (i.e.
when EN1 = 0, PWM1 is disabled, and when EN2 = 0,
PWM2 is disabled).
7
2
2
C interface
C bus by writing
2
C
2
C, then
ISL6405
When the regulator blocks are active (EN1, EN2 = HIGH),
the output can be logic controlled to be 13V or 18 V (typical)
by mean of the VSEL bit (Voltage Select) for remote
controlling of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typical) the selected voltage value to
compensate for the excess voltage drop along the coaxial
cable (LLC1/2 bit HIGH).
Output Timing
The programmed output voltage rise and fall times can be
set by an internal 25kΩ resistor and an external / internal
capacitor located on the TCAP terminal. Although any value
of capacitor is permitted, practical values are typically 0.1µf
to 1µf. This feature only affects the turn-on and programmed
voltage rise and fall times. This terminal can be left open if
output voltage rise and fall time control is not required.
Current Limiting
The current limiting block has two thresholds that can be
selected by the ISEL bit of the SR and can work either
statically (simple current clamp) or dynamically. The lower
threshold is between 425mA and 530mA (ISEL = L), while
the higher threshold is between 775mA and 925mA (ISEL =
H). When the DCL (Dynamic Current Limiting) bit is set to
LOW, the over current protection circuit works dynamically:
as soon as an overload is detected, the output is shutdown
for a time t
of the System Register is set to HIGH. After this time has
elapsed, the output is resumed for a time t
During t
425mA or 775mA, depending on the ISEL bits. At the end of
t
cycle again through t
which no overload is detected, normal operation is resumed
and the OLF bit is reset to LOW. Typical t
920ms as determined by an internal timer. This dynamic
operation can greatly reduce the power dissipation in a short
circuit condition, still ensuring excellent power-on start-up in
most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1/2
bit goes HIGH when the current clamp limit is reached and
returns LOW when the overload condition is cleared. The
OLF1/2 bit will be LOW at the end of initial power-on soft-start.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to 135°C
(typical).
ON
, if the overload is still detected, the protection circuit will
ON
OFF
, the device output will be current limited to
, typically 900ms. Simultaneously the OLF bit
OFF
and t
ON
. At the end of a full t
ON
ON
+ t
= 20ms.
OFF
time is
ON
in