ISL6420A Intersil, ISL6420A Datasheet
ISL6420A
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ISL6420A Summary of contents
Page 1
... ENSS pin to ground sets a fully adjustable PWM soft-start. Pulling the ENSS pin LOW disables the controller. The ISL6420A monitors the output voltage and generates a PGOOD (power good) signal when soft-start sequence is complete and the output is within regulation. A built-in overvoltage protection circuit prevents the output voltage from going above typically 115% of the set point ...
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... NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts ISL6420A (QFN) TOP VIEW www.DataSheet4U.com 20 ...
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... Functional Block Diagram SGND FB COMP GPIO1/REFIN GPIO2 www.DataSheet4U.com REFOUT VMSET/MODE Typical 5V Input DC/DC Application Schematic ENSS PGOOD C7 R2 0.1µF CDEL C8 SGND ISL6420A VIN VCC5 OCSET LDO PHASE REFERENCE SS 0.6V OVFLT UVFLT ERROR AMP + - + - PWM COMP RAMP GENERATOR VOLTAGE MARGINING OV/UV OVFLT FB VOLTAGE ...
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... ENSS PGOOD R2 C7 CDEL C8 SGND www.DataSheet4U.com R3 R4 Typical 5V Input DC/DC Application Schematic SS/EN RT CDEL R2 C7 PGOOD SGND CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS 4 ISL6420A C3 C4 PVCC VIN VCC5 OCSET MONITOR AND PROTECTION BOOT RT UGATE OSC PHASE REF LGATE - - + + + FB + PGND - - ...
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... Typical 12V Input DC/DC Application Schematic 12V C1 C2 SS/EN CDEL R2 C7 PGOOD SGND www.DataSheet4U.com R3 R4 CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS 5 ISL6420A C3 C4 VIN PVCC VCC5 OCSET MONITOR AND PROTECTION BOOT RT UGATE OSC PHASE REF LGATE - - + + + FB + PGND - - COMP GPIO1/REFIN <-- VREF = VDDQ/2 C10 ...
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... OSCILLATOR Free Running Frequency Total Variation Frequency Range (Set by RT) Ramp Amplitude (Note 7) 6 ISL6420A Thermal Information (Note 1) Thermal Resistance (Typical) Maximum Junction Temperature (Plastic Package 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Ambient Temperature Range -40°C to 85°C (for “I” suffix) Junction Temperature Range -40° ...
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... EXTERNAL REFERENCE MIn External Reference Input at GPIO1/REFIN. Max External Reference Input at GPIO1/REFIN. REFERENCE BUFFER Buffered Output Voltage - Internal Reference Buffered Output Voltage - Internal Reference Buffered Output Voltage - External Reference 7 ISL6420A SYMBOL TEST CONDITIONS V REF T = -40°C to 85°C, VIN = 5.6V to 28V ...
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... Guaranteed by design. Not production tested. Typical Performance Curves 0.604 0.602 0.600 0.598 0.596 0.594 -40 -15 10 TEMPERATURE (°C) FIGURE TEMPERATURE REF 8 ISL6420A SYMBOL TEST CONDITIONS 1.25V, I REFOUT REFIN REFOUT VMSET2/MODE = High 2.2µF REFOUT C = 2.2µF REFOUT CDEL = 0.1µF, VMSET = 330kΩ ...
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... Typical Performance Curves 1.15 1.05 0.95 0.85 -40 -15 10 TEMPERATURE (°C) FIGURE TEMPERATURE www.DataSheet4U.com OCSET 25° 28V 1.367 FIGURE 5. 9 ISL6420A (Continued 10A OUT 12V LOAD (A) FIGURE 7. EFFICIENCY vs LOAD CURRENT (V 94.00 92. OUT 90.00 88.00 86.00 84.00 82.00 80. ...
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... A 0.1µF will typically provide 125ms delay. When in the Voltage margining mode the CDEL current is 100µA typical and provides the delay for the output voltage slew rate, 2.5ms typical for the 0.1µF capacitor. 10 ISL6420A 1400 1300 1200 1100 1000 ...
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... For 5V ±10% applications, connect VIN to VCC5 to bypass the linear regulator. Soft-Start/Enable The ISL6420A soft-start function uses an internal current source and an external capacitor to reduce stresses and surge current during startup. When the output of the internal linear regulator reaches the POR threshold, the POR function initiates the soft-start sequence. An internal 10µ ...
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... The upper gate pulse is immediately terminated, and a counter is incremented overcurrent condition is detected for 8 consecutive clock cycles, and the circuit is not in soft-start, the ISL6420A enters into the soft- start hiccup mode. During hiccup, the external capacitor on the ENSS pin is discharged. After the cap is discharged released and a soft-start cycle is initiated ...
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... VCC5, then the internal 0.6V reference is used as the error amplifier non-inverting input. The buffered reference output on REFOUT will be 0.6V ±0.01V, capable of sourcing 13 ISL6420A 20mA and sinking up to 50µA current with a 2.2µF capacitor connected to the REFOUT pin. If VMSET/MODE pin is tied to high but GPIO1/REFIN is connected to an external voltage source between 0 ...
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... MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. Startup into Pre-Biased Load The ISL6420A is designed to power up into a pre-biased load. This is achieved by transitioning from Diode Emulation mode to a Forced Continuous Conduction mode during startup. The lower gate turns ON for a short period of time and the voltage on the phase pin is sensed ...
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... Please note that the capacitors C and C each represent numerous physical capacitors. O Locate the ISL6420A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6420A must be sized to handle peak current. ...
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... ESR C O The compensation network consists of the error amplifier (internal to the ISL6420A) and the impedance networks Z and Z . The goal of the compensation network is to provide FB a closed loop transfer function with the highest 0dB crossing frequency (f ) and adequate phase margin. Phase margin ...
Page 17
... Given a sufficiently fast control loop design, the ISL6420A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
Page 18
... These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse- recovery of the lower MOSFET’s body diode. The gate-charge losses are dissipated by the ISL6420A and don't heat the MOSFETs. However, large gate-charge increases the switching interval, t upper MOSFET switching losses ...
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... Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) www.DataSheet4U.com 19 ISL6420A L20.4x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE I) MILLIMETERS SYMBOL MIN 0. θ - NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 ISL6420A M20.15 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE 0.25(0.010) ...