ISL6420A Intersil, ISL6420A Datasheet - Page 12

• Manufacturer Part Number: ISL6420A
• Description: Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: Intersil

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Overcurrent Protection
The overcurrent function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
r
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode with an ON time of 20ms and an OFF time of
128ms to provide fault protection. On detecting an
overcurrent condition, the IC waits for four soft-start cycles
before the output drivers are turned ON again, this process
is repeated till the overcurrent condition is removed. A
resistor connected to the drain of the upper FET and the
OCSET pin programs the overcurrent trip level. The PHASE
node voltage will be compared against the voltage on the
OCSET pin, while the upper FET is on. A current (100µA
typically) is pulled from the OCSET pin to establish the
OCSET voltage. If PHASE is lower than OCSET while the
upper FET is on then an overcurrent condition is detected for
that clock cycle. The upper gate pulse is immediately
terminated, and a counter is incremented. If an overcurrent
condition is detected for 8 consecutive clock cycles, and the
circuit is not in soft-start, the ISL6420A enters into the soft-
start hiccup mode. During hiccup, the external capacitor on
the ENSS pin is discharged. After the cap is discharged, it is
released and a soft-start cycle is initiated. During soft-start,
pulse termination current limiting is enabled, but the 8-cycle
hiccup counter is held in reset until soft-start is completed.
The overcurrent function will trip at a peak inductor current
(I
internal OCSET current source.
The OC trip point varies mainly due to the upper MOSFETs
r
normal operating load range, find the R
the equation above with:
A small ceramic capacitor should be placed in parallel with
R
presence of switching noise on the input voltage.
DS(ON)
DS(ON)
1. The maximum r
2. Determine
OC
OCSET
temperature.
where ∆I is the output inductor ripple current.
) determined from Equation 1, where I
to monitor the current. This method enhances the
variations. To avoid overcurrent tripping in the
to smooth the voltage across R
I
OC
for I
DS(ON)
OC
>
at the highest junction
I
OUT MAX
12
(
)
+
OCSET
(
OCSET
∆I
OCSET
) 2 ⁄
resistor from
,
in the
is the
ISL6420A
Voltage Margining
The ISL6420A has a voltage margining mode that can be
used for system testing. The voltage margining percentage
is resistor selectable up to ±10%. The voltage margining
mode can be enabled by connecting a margining set resistor
from VMSET pin to ground and using the control pins
GPIO1/2 to toggle between positive and negative margining
(Refer to Table 2). With voltage margining enabled, the
VMSET resistor to ground will set a current, which is
switched to the FB pin. The current will be equal to 2.468V
divided by the value of the external resistor tied to the
VMSET pin.
The power supply output increases when GPIO2 is HIGH
and decreases when GPIO1 is HIGH. The amount that the
output voltage of the power supply changes with voltage
margining, will be equal to 2.468V times the ratio of the
external feedback resistor and the external resistor tied to
VMSET. Figure 10 shows the positive and negative
margining for a 3.3V output, using a 20.5kΩ feedback
resistor and using various VMSET resistor values.
I
∆
VM
FIGURE 10. VOLTAGE MARGINING vs VMSET RESISTANCE
V
VM
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
=
150
=
----------------------- -
R
2.468V
VMSET
2.468V
175
----------------------- -
R
200
VMSET
R
FB
225
250
RVMSET (kΩ)
275
300
325
350
October 13, 2005
375
FN9169.1
(EQ. 2)
(EQ. 3)
400