ISL6540 Intersil Corporation, ISL6540 Datasheet - Page 13

• Manufacturer Part Number: ISL6540
• Description: Single-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

Frequency Programming
By tying a resistor to GND from FS pin, the switching
frequency can be set between 250kHz and 2MHz.
Oscillator/VFF
The Oscillator is a triangle waveform, providing for leading
and falling edge modulation. The bottom of the oscillator
waveform is set at 1.0V. The ramp's peak to peak amplitude
is determined from the voltage on the VFF (Voltage Feed
Forward) pin by the equation: DVosc = 0.16*VFF. An internal
RC filter of 233kΩ and 2pF (341kHz) provides filtering of the
VFF voltage. An external RC filter may be required to
augment this filter in the event that it is insufficient to prevent
noise injection or control loop interactions. Voltages below
2.9V on the VFF pin may result in undesirable operation due
to extremely small peak to peak oscillator waveforms. The
oscillator waveform should not exceed VCC -1.0V. For high
VFF voltages the internal/external 5.6 V linear regulator
should be used. 5.6V on VCC provides sufficient headroom
for 100% duty cycle operation when using the maximum
VFF voltage of 22V. In the event of sustained 100% duty
cycle operation, defined as 32 clock cycles where no LG
pulse is detected, LG will be pulsed on to refresh the
design’s Bootstrap capacitor.
Internal Series Linear Regulator
The VIN pin is connected to PVCC with a 2Ω internal series
linear regulator, which is internally compensated. The
external Series Linear regulator option should be used for
applications requiring pass elements of less than 2Ω. When
using the internal regulator, the LIN_DRV pin should be
connected directly to GND. The PVCC and VIN pins should
have a bypasses capacitor (at least 10µF on PVCC is
required) connected to PGND. For proper operation the
PVCC capacitor must be within 150mils of the PVCC and the
PGND pins, and be connected to these pins with dedicated
traces. The internal series linear regulator’s input (VIN) can
Fs Hz
[
100
10
]
1
≈
FIGURE 4. R
100
1.178
×10
10
•
FS
R
T
RESISTANCE vs. FREQUENCY
[ ]
FREQUENCY (kHz)
Ω
–
0.973
13
1000
(R
T
TO GND)
10000
ISL6540
range between 3.3V to 20V ±10%. The internal linear
regulator is to provide power for both the internal MOSFET
drivers through the PVCC pin and the analog circuitry
through the VCC pin. The VCC pin should be connected to
the PVCC pin with an RC filter to prevent high frequency
driver switching noise from entering the analog circuitry.
When VIN drops below 5.6V, the pass element will saturate;
PVCC will track VIN, minus the dropout of the linear
regulator: PVCC = VIN-2xI
5V supply, the VIN pin should be tied directly to PVCC.
External Series Linear Regulator
The LIN_DRV pin provides sinking drive capability for an
external pass element linear regulator controller. The
external linear options are especially useful when the
internal linear dropout is too large for a given application.
When using the external linear regulator option, the
LIN_DRV pin should be connected to the gate of a PMOS
device, and a resistor should be connected between its gate
and source. A resistor and a capacitor should be connected
from gate to source to compensate the control loop. A PNP
device can be used instead of a PMOS device in which case
the LIN_DRV pin should be connected to the base of the
PNP pass element. The maximum sinking capability of the
LIN_DRV pin is 0.5mA, and should not be exceeded if using
an external resistor for a PMOS device. The designer should
take care in designing a stable system when using external
pass elements. The VCC pin should be connected to the
PVCC pin with an RC filter to prevent high frequency driver
switching noise from entering the analog circuitry.
High Speed MOSFET Gate Driver
The integrated driver has similar drive capability and
features to Intersil's ISL6605 stand alone gate driver. The
PWM tri-state feature helps prevent a negative transient on
the output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the microprocessor from reversed-output-
voltage damage. See the ISL6605 datasheet for
specification parameters that are not defined in the current
ISL6540 electrical specifications table.
A 1-2Ω resistor is recommended to be in series with the
bootstrap diode when using VCCs above 5.0V to prevent the
bootstrap capacitor from overcharging due to the negative
swing of the trailing edge of the phase node.
Margining Control
When the MAR_CTRL is pulled high or low, the positive or
negative margining functionality is respectively enabled.
When MAR_CTRL is left floating, the function is disabled.
Upon UP margining, an internal buffer drives the OFS- pin
from VCC to maintain OFS+ at 0.591V. The resistor divider,
R
increased. Similarly, upon DOWN margining, an internal
buffer drives the OFS+ pin from VCC to maintain OFS- at
0.591V. The resistor divider, R
MARG
and R
OFS+
, causes the voltage at OFS- to be
VIN
. When used with an external
MARG
and R
OFS-
, causes the
March 9, 2006
FN9214.0