ISL6540 Intersil Corporation, ISL6540 Datasheet - Page 16

• Manufacturer Part Number: ISL6540
• Description: Single-Phase Buck PWM Controller
• Manufacturer: Intersil Corporation

Figure 8 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS pin and locate the capacitor, C
close to the SS pin (as described earlier) as the internal
current source is only 38µA. Provide local decoupling
between PVCC and PGND pins as described earlier. Locate
the capacitor, C
PHASE pins.
Compensating the Converter
The ISL6540 single-phase converter is a voltage-mode
controller. This section highlights the design considerations for
a voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
(V
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a pulse-
width modulated wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
DC gain, given by d
output filter, with a double pole break frequency at F
zero at F
represent the total output capacitance and its equivalent
series resistance.
F
LC
OUT
FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6540
=
) is regulated to the reference voltage, VREF, level.
---------------------------
2π
C
CE
R
3
⋅
3
1
. For the purpose of this analysis C and ESR
L C
OUT
⋅
WHEN USING DIFFERENTIAL REMOTE SENSE
BOOT
/V
COMP
MAX
R
R
as close as practical to the BOOT and
1
2
V
. This function is dominated by a
F
IN
C
CE
2
/V
C
16
=
OSC
1
-------------------------------- -
2π C ESR
, and shaped by the
⋅
COMP
VMON
1
FB
⋅
IN
ISL6540
at the
LC
and a
SS
ISL6540
The compensation network consists of the error amplifier
(internal to the ISL6540) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R
and C
locating the poles and zeros of the compensation network:
1. Select a value for R
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
value for R
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 10), in order
to compensate for the attenuation introduced by the
resistor divider, the below obtained R
multiplied by a factor of (R
of the calculations remain unchanged, as long as the
compensated R
CIRCUIT
PWM
3
) in Figures 9 and 10. Use the following guidelines for
COMP
0
COMPENSATION DESIGN
; typically 0.1 to 0.3 of F
2
HALF-BRIDGE
OSCILLATOR
for desired converter bandwidth (F
V
OSC
E/A
DRIVE
2
R
value is used.
ISL6540
2
1
C
+
-
+
(1kΩ to 10kΩ, typically). Calculate
VREF
2
-
C
1
OS
FB
PHASE
UGATE
LGATE
VMON
VSEN-
VSEN+
+R
EXTERNAL CIRCUIT
FB
SW
R
)/R
3
V
IN
) and adequate
R
2
OS
C
1
1
1
SEN
value needs be
, R
-R
C
. The remainder
L
3
0dB
3
2
, C
, R
DCR
R
and 180°.
V
1
3
ESR
March 9, 2006
OS
OUT
-C
0
, C
C
). If
R
3
FB
FN9214.0
1
, C
2
,