ISL9208 Intersil Corporation, ISL9208 Datasheet
ISL9208
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ISL9208 Summary of contents
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... Data Sheet Multi-Cell Li-ion Battery Pack OCP/Analog Front End The ISL9208 is an overcurrent protection device and analog front end for a microcontroller in a multi-cell Li-ion battery pack. The ISL9208 supports battery pack configurations consisting of 5 cells to 7 cells in series and 1 or more cells in parallel ...
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... VC7/VCC CB7 VCELL6 CB6 VCELL5 LEVEL CB5 SHIFTERS/ VCELL4 CELL BALANCE CB4 CIRCUITS VCELL3 CB3 VCELL2 CB2 VCELL1 CB1 BACKUP SUPPLY VSS 2 ISL9208 ISL9208 (32 LD QFN) TOP VIEW VC7/VCC 3 CB7 4 VCELL6 5 CB6 6 VCELL5 CB5 7 VCELL4 ...
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... N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9208 also turns off the FET in the event of an overcurrent or short circuit condition. If the microcontroller detects an undervoltage condition on any of the battery cells, it can turn off the discharge FET by controlling this output with a control bit ...
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... Regulated output voltage. This pin connects to the emitter of an external NPN transistor and works in conjunction with the RGC pin to provides a regulated 3.3V. The voltage at this pin provides feedback for the regulator and power for many of the ISL9208 internal circuits as well as providing the 3.3V output voltage for the microcontroller and other external circuits. ...
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... RGO Supply Current V Supply Current CC RGO Supply Current VCELL Input Current - V CELL1 VCELL Input Current - V CELLN 5 ISL9208 Thermal Information - 0. 36.0V Thermal Resistance (Typical, Note QFN . . . . . . . . . . . . . . . . . . . . . . Continuous Package Power Dissipation . . . . . . . . . . . . . . . . .400mW Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C Lead temperature (soldering 10s +300°C -0 ...
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... Boldface) Load Monitor Input Threshold (Falling Edge) Load Monitor Input Threshold V (Hysteresis) Load Monitor Current Short Circuit Time-out Over Discharge Current Time-out (Default In Boldface) 6 ISL9208 TEST CONDITION 0.10V (OCDV1, OCDV0 = 0, 0) OCD OCD V = 0.12V (OCDV1, OCDV0 = 0,1) OCD V = 0.14V (OCDV1, OCDV0 = 1,0) ...
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... External Temperature Output Current External Temperature Limit Threshold External Temperature Limit Hysteresis External Temperature Monitor Delay External Temperature Autoscan On Time External Temperature Autoscan Off Time 7 ISL9208 TEST CONDITION 64ms (OCCT1,OCCT0 = 0, 0 and OCC OCC CTDIV = 128ms (OCCT1, OCCT0 = 0, 1 and ...
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... Control Outputs Response Time (CFET, DFET) CFET Gate Voltage DFETGate Voltage FET Turn On Current (DFET) FET Turn On Current (CFET) FET Turn Off Current (DFET) I DFET Resistance to VSS R 8 ISL9208 TEST CONDITION )]/ AOC CELLN CELLN-1 V External temperature monitoring accuracy. AOXT ...
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... The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL. 5. Typical +125°C ±10%, based on design and characterization data. 6. Typical 5Ω ±2Ω, based on design and characterization data. 7. Maximum output capacitance = 15pF. 9 ISL9208 TEST CONDITION f SCL t ...
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... WKUP2 WKUP PIN t WKUP WKUP BIT Wake up timing (WKPOL = 1) <t WKUP V WKUP1 WKUP PIN t WKUP WKUP BIT Change in Voltage Source, FET Control SCL BIT SDA 3 AO DFET CFET 10 ISL9208 <t WKUP <t WKUP BIT BIT BIT DATA t VSC WKUP2H t WKUP V WKUP1H ...
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... DSENSE t SCD ‘0’ DOC BIT ‘0’ DSC BIT TEMP3V OUTPUT VCELL3 DFET OUTPUT 11 ISL9208 508ms 3.3V HIGH IMPEDANCE THRESHOLD DELAY TIME = 1ms MONITOR TEMP DURING THIS TIME PERIOD (assumes DENOCD and DENSCD bits are ‘0’) t OCD ‘1’ 3.3V REGISTER 1 READ ...
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... HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM LOW TO HIGH MAY CHANGE FROM HIGH TO LOW 12 ISL9208 (assumes DENOCC bit is ‘0’) t OCC ‘1’ 3.3V REGISTER 1 READ HIGH LOW t t SU:DAT HD:DAT ...
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... When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns 2 off the FETs. At all other times write operation controls the output to the respective FET and a read returns the current state of the FET drive output circuit (though not the actual voltage at the output pin.) 13 ISL9208 TABLE 1. REGISTERS Reserved ...
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... RESERVED Reserved for future expansion. 6 RESERVED Reserved for future expansion Indicates the device is an ISL9208. This bit is set in the chip and cannot be changed. Single AFE 4 WKUP This bit is set and reset by hardware. Wakeup pin status When ‘WKPOL’ is HIGH: ’WKUP’ HIGH = WKUP pin > Threshold voltage ‘ ...
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... UFLG0 User Flag 0 5:4 RESERVED Bit 3 Bit 2 AO3 AO2 ISL9208 CONTROL REGISTER BITS BIT 4 BIT 3 CB4ON CB3ON ...
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... ISL9208 This memory is powered by the RGO output sleep condition, an internal switch converts power for the contents of these registers from RGO to the VCELL1 input. TABLE 6. FET CONTROL REGISTER (ADDR: 04H) Setting this bit to “1” forces the device to go into a sleep condition. This turns off both FET outputs, the cell balance outputs and the voltage regulator. This also resets the CFET, DFET, and CB7ON:CB1ON bits. The SLEEP bit is automatically reset to “ ...
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... WKPOL Wake Up Polarity 17 ISL9208 When set to ‘0’, a charge overcurrent condition automatically turns off the FETs. When set to ‘1’, a charge overcurrent condition will not automatically turn off the FETs. In either case, this condition sets the COC bit, which also turns on the TEMP3V output. ...
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... The ISL9208 powers up when the voltages CELL2 At this time, the ISL9208 wakes up and turns on the RGO output. RGO provides a regulated 3.3VDC ±10% voltage at pin RGO. It does this by using a control voltage on the RGC pin to drive an external NPN transistor (See Figure 2.) The ...
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... WKUP Pin Operation There are two ways to design a wake up of the ISL9208 active LOW connection (WKPOL = “0” - default), the device wakes up when a charger is connected to the pack. This pulls the WKUP pin low when compared to a reference based on the V voltage active HIGH connection CELL1 (WKPOL = ‘ ...
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... LDMONEN VSS FIGURE 4. LOAD MONITOR CIRCUIT LOAD MONITORING The load monitor function in the ISL9208 (see Figure 4) is used primarily to detect that the load has been removed following an overcurrent or short circuit condition during discharge. This can be used in a control algorithm to prevent the FETs from turning on while the overload or short circuit condition remains ...
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... Analog Multiplexer Selection The ISL9208 devices can be used to externally monitor individual battery cell voltages and temperatures. Each quantity can be monitored at the analog output pin (AO). The desired voltage is selected using the I AO3:AO0 bits ...
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... CFET pin. So recommended that an additional external series diode be placed between the CFET pin of the ISL9208 and the gate of the Charge FET. See Diode D3 in Figure 8. This will reduce the CFET gate voltage, but not significantly. ...
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... User Flags The ISL9208 contains four flags in the register area that the microcontroller can use for general purpose indicators. These bits are designated UFLG3, UFLG2, UFLG1, and UFLG0. The microcontroller can set or reset these bits by writing into the appropriate register. The user flag bits are battery backed up, so the contents remain even after exiting a sleep mode ...
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... Feature Set register (Address 5). The microcontroller can reset these bits back to zero to prevent inadvertent writes that change the operation of the pack. Operation State Machine Figure 14 shows a device state machine which defines how the ISL9208 responds to various conditions SLAVE R ...
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... CONDITIONS FORCE POWER FETS AND CELL BALANCE OUTPUTS TO TURN OFF. VOLTAGE AND TEMPERATURE MONITORING CIRCUITS ARE AWAITING EXTERNAL CONTROL. FIGURE 14. DEVICE OPERATION STATE MACHINE 25 ISL9208 DO NOT MEET MINIMUM VOLTAGE REQUIREMENTS POWER DOWN STATE INTERFACE IS DISABLED. BIASING IS DISABLED. ALL REGISTERS SET TO DEFAULT VALUES (ALL “ ...
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... CB2 4.7µF VCELL1 CB1 MINIMIZE LENGTH MAXIMIZE GAUGE V SS DSREF B- FIGURE 15. 7-CELL APPLICATION CIRCUIT INTEGRATED CHARGE/DISCHARGE 26 ISL9208 Also refer to the ISL9208, ISL9216, ISL9217 application guide for additional circuit design guidelines. 10M SCL SDA WKUP RGC 1µF RGO V CC µC RESET TEMP3V ...
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... VCELL3 TEMPI CB3 VCELL2 AO CB2 4.7µF VCELL1 VMON CB1 CFET MINIMIZE LENGTH DFET MAXIMIZE GAUGE V SS DSREF OPTIONAL B- FIGURE 16. 7-CELL APPLICATION CIRCUIT SEPARATE CHARGE/DISCHARGE 27 ISL9208 500 10M 1µF V µC CC RESET OPTIONAL GP LEDS I/O RESISTORS SCL SDA INT 100 A/D INPUT I/O 3.6V ONE-WIRE INTERFACE NOT NEEDED DURING ...
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... VCELL2 AO CB2 4.7µF VCELL1 VMON CB1 CFET MINIMIZE LENGTH DFET MAXIMIZE GAUGE V SS DSREF OPTIONAL B- FIGURE 17. 7-CELL APPLICATION CIRCUIT WITH SWITCH WAKE-UP AND SEPARATE CHARGE/DISCHARGE 28 ISL9208 825k 500 10V 1µ µC RESET OPTIONAL GP LEDS I/O RESISTORS SCL SDA INT 100 A/D INPUT I/O 3 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 ISL9208 L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C ...