ISL9208 Intersil Corporation, ISL9208 Datasheet - Page 24

• Manufacturer Part Number: ISL9208
• Description: Multi-Cell Li-ion Battery Pack OCP/Analog Front End
• Manufacturer: Intersil Corporation

WRITE OPERATIONS
For a write operation, the device requires a slave byte and
an address byte. The slave byte specifies the particular
device on the I
address specifies one of the registers in that device. After
receipt of each byte, the device responds with an
acknowledge, and awaits the next eight bits from the master.
After the acknowledge, following the transfer of data, the
master terminates the transfer by generating a stop
condition. See Figure 12.
When receiving data from the master, the value in the data
byte is transferred into the register specified by the address
byte on the falling edge of the clock following the 8th data bit.
After receiving the acknowledge after the data byte, the
device automatically increments the address. So, before
sending the stop bit, the master may send additional data to
the device without re-sending the slave and address bytes.
After writing to address 0AH, the address “wraps around” to
address 0. Do not continue to write to addresses higher than
address 08H, since these addresses access registers that
are reserved. Writing to these locations can result in
unexpected device operation.
Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the last bit of the slave
byte is set to one. After the device acknowledges the register
address, it sends out one bit of data for each master clock.
After sending eight bits to the master, the master sends a
NACK (Not acknowledge) to the device, then sends a stop
bit. See Figure 13.
After sending the eighth data bit to the master, the device
automatically increments its internal address pointer. So the
master, instead of sending the stop bit, can send additional
clocks to read the contents of the next register-without
sending another slave and address byte. After reading from
address 9, the device address wraps around to 0, so
continued master clocks would allow an indefinite number of
reads from the device.
.
2
C bus that the master is writing to. The
24
ISL9208
Register Protection
The Discharge Set, Charge Set, and Feature Set
configuration registers are write protected on initial power
up. In order to write to these registers it is necessary to set a
bit to enable each one. These write enable bits are in the
Write Enable register (Address 08H).
Write the FSETEN bit (Addr 8:bit 7) to “1” to enable changes
to the data in the Feature Set register (Address 7).
Write the CHSETEN bit (Addr 8:bit 6) to “1” to enable
changes to the data in the Feature Set register (Address 6).
Write the DISSETEN bit (Addr 8:bit 5) to “1” to enable
changes to the data in the Feature Set register (Address 5).
The microcontroller can reset these bits back to zero to
prevent inadvertent writes that change the operation of the
pack.
Operation State Machine
Figure 14 shows a device state machine which defines how
the ISL9208 responds to various conditions.
SDA BUS
SDA
BUS
A
R
A
R
S
T
T
S
T
T
0 1 0 1
0 1 0 1
FIGURE 12. WRITE SEQUENCE
SLAVE
SLAVE
FIGURE 13. READ SEQUENCE
BYTE
BYTE
0
0
ISL9208: SLAVE BYTE = 51H
0 0
0 0
ISL9208: SLAVE BYTE = 50H
0
1
A
C
K
A
C
K
REGISTER
REGISTER
ADDRESS
ADDRESS
A
C
K
A
C
K
DATA
DATA
February 16, 2007
FN6446.0
A
C
K
N
A
C
K
S
O
P
S
O
P
T
T