ISL95311 Intersil Corporation, ISL95311 Datasheet - Page 4

• Manufacturer Part Number: ISL95311
• Description: 128 Taps I2C Interface
• Manufacturer: Intersil Corporation

Operating Specifications
EEPROM SPECS
SERIAL INTERFACE SPECS
Hysteresis
SYMBOL
VccRamp
(Note 13)
(Note 13)
(Note 10)
(Note 13)
t
t
I
SU:STA
HD:STA
LkgDig
t
t
t
I
I
Vpor
Cpin
f
t
V
HIGH
LOW
DCP
V
CC1
CC2
I
V
SCL
t
BUF
I
t
SB
V+
t
AA
OL
IN
D
IH
IL
V
V
V
V+ bias current
Leakage current, at pins SDA, SCL,
A0, and A1 pins
DCP wiper response time
Power-on recall voltage
V
Power-up delay
EEPROM endurance
EEPROM retention
A0, A1, SDA, and SCL input buffer
LOW voltage
A0, A1, SDA, and SCL input buffer
HIGH voltage
SDA and SCL input buffer hysteresis
SDA output buffer LOW voltage,
sinking 4mA
A0, A1, SDA, and SCL pin
capacitance
SCL frequency
Pulse width suppression time at SDA
and SCL inputs
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
Clock LOW time
Clock HIGH time
START condition setup time
START condition hold time
CC
CC
CC
CC
supply current, volatile write/read f
supply current, nonvolatile write
current, standby
ramp rate
PARAMETER
4
Over the recommended operating conditions unless otherwise specified.
read, and volatile write states only)
f
nonvolatile write states only)
V
V
V+ = 13.2V, V
Voltage at pin from GND to V
SCL falling edge of last bit of DCP data byte to
wiper change
Minimum V
V
recall completed, and I
state
Temperature ≤ 75°C
Any pulse narrower than the max spec is
suppressed
SCL falling edge crossing 30% of V
exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge; both
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
SCL
SCL
CC
CC
CC
= +5.5V, I
= +3.6V, I
above Vpor, to DCP initial value register
= 400kHz; SDA = Open; (for I
= 400kHz; SDA = Open; (for I
ISL95311
CC
TEST CONDITIONS
CC
2
2
at which memory recall occurs
C interface in standby state
C interface in standby state
= +5.5V
CC
2
CC
C Interface in standby
CC
CC
CC
during a STOP
CC
window
crossing
crossing
CC
2
2
CC
C, active,
C, active,
CC
, until SDA
during
CC
to
200,000
0.05*
1300
1300
V
V
MIN
0.7*
-0.3
600
600
600
-10
1.8
0.2
50
CC
CC
0
(Note 1)
TYP
V
MAX
V
0.3*
400
900
2.6
0.3
0.4
CC
10
10
50
1
3
5
2
1
1
3
CC
+
May 6, 2005
Cycles
Years
UNIT
V/ms
FN8084.0
kHz
mA
mA
ms
µA
µA
µA
µA
pF
µs
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
V