80C154 TEMIC Semiconductors, 80C154 Datasheet - Page 11

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80C154

Manufacturer Part Number
80C154
Description
CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
Manufacturer
TEMIC Semiconductors
Datasheet
Rev.F (14 Jan. 97)
32 Bit Counter
Figure 13 illustrates the 32 bit COUNTER mode.
Watchdog Mode
MATRA MHS
Figure 12. 32 Bit Counter Configuration.
Figure 13. Counter Incrementation Condition.
In this mode, T32 = 0 and C/T0 = 1. Before it can
make an increment, the 83C154 must detect two
transitions on its T0 input. As shown in figure 14,
The counter will only evolve if a level 1 is detected
during state S5P2 of cycle Ci and if a level 0 is
detected during state S5P2 of cycle Ci + n.
Consequently, the minimal period of signal fEXT
admissible by the counter must be greater than or
equal to two machine cycles. The following formula
should be used to calculate the operating frequency.
WDT = 1 enables access to this mode. As shown in
figure 15, all the modes of TIMERS 0 and 1, of which
the overflows act on TF1 (TF1 = 1), activate the
WATCHDOG Mode.
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Figure 14. The Different Watchdog Configurations.
input T0 is sampled on each S5P2 state of every
machine cycle or, in other words, every OSC 12.
80C154/83C154
11

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