80C154 TEMIC Semiconductors, 80C154 Datasheet - Page 12

• Manufacturer Part Number: 80C154
• Description: CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
• Manufacturer: TEMIC Semiconductors

80C154/83C154
12
Table 3. Content of the SFRS after a reset triggered
REGISTER
PC
ACC
B
PSW
SP
DPTR
P0-P3
IP
IE
TMOD
TCON
T2CON
TH0
TL0
TH1
TL1
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
IOCON
PCON
If C/T = 0, the WATCHDOG is a TIMER that is
incremented every machine cycle. If C/T = 1, the
WATCHDOG is a counter that is incremented by an
external signal of which the frequency cannot exceed
OSC 24.
The overflow of the TIMER/COUNTER is signalled
by raising flag TF1 to 1. The reset of the 83C154 is
executed during the next machine cycle and lasts for
the next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal
RAM is not affected and the special register assume
the values shown in Table 3.
by the watchdog.
Indeterminate
0X000000B
0X000000B
000X0000B
CONTENT
0000H
0FFH
000H
00H
00H
00H
07H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
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External Counting in Power-down Mode
(PD = PCON.1 = 1)
As there are no precautions for protecting bit WDT
from spurious writing in the IOCON register, special
care must be taken when writing the program. In
particular, the user should use the IOCON register bit
handling instructions :
– SETB and CLR x
– MOV IOCON, # XXH, ORL IOCON, #XXH,
– ANL IOCON, #XXH
In the power-down mode, the oscillator is turned off
and the 83C154’s activity is frozen. However, if an
external clock is connected to one of the two inputs,
T1/T0, TIMER/COUNTERS 0 and 1 can continue to
operate.
In this case, counting becomes asychronous and the
maximum, admissible frequency of the signal is
OSC : 24.
The overflow of either counter TF0 or TF1 causes an
interrupt to be serviced or forces a reset if the counter
is in the WATCHDOG MODE (T32 = ICON.7 = 1).
in preference to the byte handling instructions :
Rev.F (14 Jan. 97)
MATRA MHS