MACH211SP-10 Advanced Micro Devices, MACH211SP-10 Datasheet - Page 7

• Manufacturer Part Number: MACH211SP-10
• Description: High-Density EE CMOS Programmable Logic
• Manufacturer: Advanced Micro Devices

FUNCTIONAL DESCRIPTION
The MACH211SP consists of four PAL blocks con-
nected by a switch matrix. There are 32 I/O pins feeding
the switch matrix. These signals are distributed to the
four PAL blocks for efficient design implementation.
There are two clock pins that can also be used as ded-
icated inputs.
The PAL Blocks
Each PAL block in the MACH211SP (Figure 1) contains
a 64-product-term logic array, a logic allocator, 8 output
macrocells, 8 buried macrocells, and 8 I/O cells. The
switch matrix feeds each PAL block with 26 inputs. This
makes the PAL block look effectively like an indepen-
dent “PAL26V16” with 8 buried macrocells.
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are pro-
vided. One of the two output enable product terms can
be chosen within each I/O cell in the PAL block. All
flip-flops within the PAL block are initialized together.
The Switch Matrix
The MACH211SP switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 16 internal feedback signals and 8 I/O feed-
back signals. The switch matrix distributes these sig-
nals back to the PAL blocks in an efficient manner that
also provides for high performance. The design soft-
ware automatically configures the switch matrix when
fitting a design into the device.
The Product-term Array
The MACH211SP product-term array consists of 64
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable; one pro-
vides asynchronous reset, and one provides asynchro-
nous preset.
The Logic Allocator
The logic allocator in the MACH211SP takes the 64
logic product terms and allocates them to the 16
macrocells as needed. Each macrocell can be driven
by up to 16 product terms. The design software auto-
matically configures the logic allocator when fitting the
design into the device.
Table 1 illustrates which product term clusters are avail-
able to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
The Macrocell
The MACH211SP has two types of macrocell: output
and buried. The output macrocells can be configured
as either registered, latched, or combinatorial, with pro-
grammable polarity. The macrocell provides internal
MACH211SP-7/10/12/15/20
feedback whether configured with or without the
flip-flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of two clock/
gate pins, which are also available as data inputs. The
registers are clocked on the LOW-to-HIGH transition of
the clock signal. The latch holds its data when the gate
input is HIGH, and is transparent when the gate input
is LOW. The flip-flops can also be asynchronously ini-
tialized with the common asynchronous reset and pre-
set product terms.
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
The I/O Cell
The I/O cell in the MACH211SP consists of a
three-state output buffer. The three-state buffer can be
configured in one of three ways: always enabled, al-
ways disabled, or controlled by a product term. If prod-
uct term control is chosen, one of two product terms
may be used to provide the control. The two product
terms that are available are common to all I/O cells in a
PAL block.
Output
M
M
M
M
M
M
M
M
10
12
14
0
2
4
6
8
Macrocell
Table 1. Logic Allocation
Buried
M
M
M
M
M
M
M
M
11
13
15
1
3
5
7
9
Available Clusters
C
C
C
C
C
C
10
11
12
C
C
C
C
C
C
C
9
C
8
7
, C
0
1
2
3
4
5
6
, C
, C
, C
, C
C
13
, C
, C
, C
, C
, C
, C
, C
, C
C
0
10
, C
, C
9
11
12
13
14
8
1
2
3
4
5
6
7
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
14
1
10
, C
9
11
, C
2
3
4
5
6
7
8
12
13
14
15
, C
, C
, C
, C
, C
, C
, C
, C
, C
, C
2
, C
, C
, C
15
10
4
5
6
7
8
9
11
3
12
13
14
15
7