MACH435-12 Lattice, MACH435-12 Datasheet
MACH435-12
Available stocks
Related parts for MACH435-12
MACH435-12 Summary of contents
Page 1
... FINAL MACH435-12/15/20, Q-20/25 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins in PLCC 128 Macrocells 12 ns tPD 83.3 MHz fCNT 70 Inputs with pull-up resistors 64 Outputs 192 Flip-flops — 128 Macrocell flip-flops — 64 Input flip-flops product terms per function, with XOR GENERAL DESCRIPTION The MACH435 is a member of our high-performance EE CMOS MACH 4 family ...
Page 2
... Clock Generator 2 I2, I5 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 MACH435-12/15/20, Q-20/25 OE Clock Generator OE Clock Generator OE Clock Generator OE Clock Generator 17469E-1 ...
Page 3
... GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage PLCC MACH435-12/15/20, Q-20/ GND 73 I/O55 72 I/O54 71 I/O53 70 I/O52 69 I/O51 68 I/O50 67 I/O49 66 I/O48 65 CLK / GND CLK /I 2 ...
Page 4
... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. MACH435-12/15/20, Q-20/25 OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) PACKAGE TYPE ...
Page 5
... It also makes in possible to emulate all flip-flop types with a D-type flip-flop. Register type emulation is automatically handled by the design software. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. MACH435-12/15/20, Q-20/25 5 ...
Page 6
... Each I/O cell can take its input from one of eight macrocells. The three-state buffer is controlled by an individual product term. The input flip-flop can be configured as a register or latch. Both the direct I/O signal and the registered/latched signal are available to the input switch matrix, and can be used simultaneously if desired. MACH435-12/15/20, Q-20/25 ...
Page 7
... Input 24 Switch Matrix Figure 1. MACH435 PAL Block MACH435-12/15/20, Q-20/25 Clock Generator Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell M9 M10 C10 Macrocell M10 M11 C11 M11 Macrocell M12 C12 ...
Page 8
... 5 =25 MHz Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435-12 (Com’l) ) Operating + with +4. +5.25 V Min Typ = Min 2.4 2.0 – mA) 255 OUT = 25 C (Note 5) A Typ = 5 ...
Page 9
... Input Register Setup Time SIR t Input Register Hold Time HIR t Input Register Clock to Combinatorial Output ICO External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) MACH435-12 (Com’l) -12 Min Max Unit D-type 5 ns T-type ...
Page 10
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 10 D-type T-type LOW HIGH MACH435-12 (Com’l) -12 Min Max Unit ...
Page 11
... OUT CC f =25 MHz (Note 5) A Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 –100 –100 –30 –160 255 Typ = 5 ...
Page 12
... D-type 10 T-type LOW 6 HIGH 6 D-type COS T-type 47.6 D-type 66.6 ) CNTS T-type 62.5 1/( 83.3 WLS WHS MACH435-15/20 (Com’l) -20 Max Min Max Unit 31.2 MHz 30.3 MHz 37 MHz 35.7 MHz 41.7 MHz ...
Page 13
... This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. -15 Min D-type 15 T-type 16 LOW 6 HIGH 6 1/( 83.3 WICL WICH MACH435-15/20 (Com’l) -20 Max Min Max Unit 62.5 MHz ...
Page 14
... 5 =25 MHz Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435Q-20 (Com’l) ) Operating + with +4. +5.25 V Min Typ = Min 2.4 2.0 – mA) 115 OUT = 25 C (Note 5) A Typ = 5 ...
Page 15
... Input Register Setup Time SIR t Input Register Hold Time HIR t Input Register Clock to Combinatorial Output ICO External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) MACH435Q-20 (Com’l) -20 Min Max Unit D-type 10 ns T-type ...
Page 16
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 16 D-type T-type LOW HIGH MACH435Q-20 (Com’l) -20 Min Max Unit ...
Page 17
... V = 5.0 V, OUT CC f=25 MHz (Note 5) A Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435Q-25 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 115 Typ = ...
Page 18
... SA COA T-type D-type ) CNTA T-type 1/( WLA WHA D-type T-type LOW HIGH D-type 1/( COS T-type D-type ) CNTS T-type 1/( MACH435Q-25 (Com’l) -25 Min Max Unit 21.7 MHz 21.3 MHz 24.4 MHz 23.8 MHz 26.3 MHz ...
Page 19
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. D-type T-type LOW HIGH 1/( WICL WICH MACH435Q-25 (Com’l) -25 Min Max Unit ...
Page 20
... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH435-12/15/20, Q-20/ 1.0 17469E (V) OH 17469E 17469E-6 ...
Page 21
... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH435Q Frequency (MHz) MACH435-12/15/20, Q-20/25 MACH435 17469E-7 21 ...
Page 22
... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 22 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH435-12/15/20, Q-20/25 Typ PLCC Unit 5 C/W 20 ...
Page 23
... Gate t WL 17469E- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 17469E-13 MACH435-12/15/20, Q-20/ 17469E PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS ...
Page 24
... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH435-12/15/20, Q-20/ IGO V T 17469E-15 t PDLL SLL V ...
Page 25
... Gate t WICL 17469E-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 17469E- Outputs + V OL Output Disable/Enable MACH435-12/15/20, Q-20/25 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 17469E- 17469E- APR ...
Page 26
... Apply Output Commercial 300 390 5 pF MACH435-12/15/20, Q-20/25 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 17469E-22 Measured ...
Page 27
... Min Pattern Data Retention Time Max Reprogramming Cycles 28 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min 10 20 100 MACH435-12/15/20, Q-20/25 Units Test Conditions Years Max Storage Temperature Years Max Operating Temperature Cycles Normal Programming Conditions ...
Page 28
... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH435-12/15/20, Q-20/25 CC 100 17469E-24 29 ...
Page 29
... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH435-12/15/20, Q-20/25 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...
Page 30
... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH435-12/15/20, Q-20/25 Preloaded HIGH Preloaded HIGH 17469E-26 17469E-27 31 ...