MACH435-15JC Lattice, MACH435-15JC Datasheet
MACH435-15JC
Specifications of MACH435-15JC
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MACH435-15JC Summary of contents
Page 1
... I/O pins. The MACH435 has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synchronous and asynchronous logic COM’L: -12/15/20, Q-20/25 Flexible clocking — ...
Page 2
... Clock Generator 2 I2, I5 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 MACH435-12/15/20, Q-20/25 OE Clock Generator OE Clock Generator OE Clock Generator OE Clock Generator 17469E-1 ...
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... Note: Pin-compatible with MACH130, MACH131, MACH230, and MACH231 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage PLCC MACH435-12/15/20, Q-20/ GND 73 I/O55 72 I/O54 71 I/O53 70 I/O52 69 I/O51 68 I/O50 67 I/O49 66 I/O48 65 CLK / GND CLK / I/O47 60 I/O46 59 I/O45 58 I/O44 ...
Page 4
... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. MACH435-12/15/20, Q-20/25 OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) PACKAGE TYPE ...
Page 5
... The initialization product terms provide asynchronous reset or preset to synchronous-mode macrocells in the PAL block. The Logic Allocator The logic allocator in the MACH435 takes the 80 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven product terms if in synchronous mode product terms if in asynchronous mode ...
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... The I/O Cell The I/O cell in the MACH435 consists of a three-state buffer and an input flip-flop. The I/O cell is driven by one of the macrocells, as selected by the output switch matrix. Each I/O cell can take its input from one of eight macrocells ...
Page 7
... Input 24 Switch Matrix Figure 1. MACH435 PAL Block MACH435-12/15/20, Q-20/25 Clock Generator Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell M9 M10 C10 Macrocell M10 M11 C11 M11 Macrocell M12 C12 Macrocell M12 M13 C13 Macrocell M13 M14 C14 Macrocell ...
Page 8
... V (Note 0 Max (Note 4) OUT Outputs Open ( 5 =25 MHz Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435-12 (Com’l) ) Operating + with +4. +5.25 V Min Typ = Min 2.4 2.0 – mA) 255 OUT = 25 C (Note 5) A Typ = 5 Max Unit V 0 0.8 V ...
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... Transparent Input or Output Latch t Input Register Setup Time SIR t Input Register Hold Time HIR t Input Register Clock to Combinatorial Output ICO External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) MACH435-12 (Com’l) -12 Min Max Unit D-type 5 ns T-type LOW ...
Page 10
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 10 D-type T-type LOW HIGH MACH435-12 (Com’l) -12 Min Max Unit ...
Page 11
... Max (Note 4) OUT Outputs Open mA 5.0 V, OUT CC f =25 MHz (Note 5) A Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 –100 –100 –30 –160 255 Typ = 5 Unit ...
Page 12
... D-type 47.6 ) CNTA T-type 45.4 1/( 55.6 WLA WHA D-type 10 T-type LOW 6 HIGH 6 D-type COS T-type 47.6 D-type 66.6 ) CNTS T-type 62.5 1/( 83.3 WLS WHS MACH435-15/20 (Com’l) -20 Max Min Max Unit 31.2 MHz 30.3 MHz 37 MHz 35.7 MHz 41.7 MHz MHz 38 ...
Page 13
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. -15 Min D-type 15 T-type 16 LOW 6 HIGH 6 1/( 83.3 WICL WICH MACH435-15/20 (Com’l) -20 Max Min Max Unit 62.5 MHz ...
Page 14
... V (Note 0 Max (Note 4) OUT Outputs Open ( 5 =25 MHz Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435Q-20 (Com’l) ) Operating + with +4. +5.25 V Min Typ = Min 2.4 2.0 – mA) 115 OUT = 25 C (Note 5) A Typ = 5 Max Unit V 0 0.8 V ...
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... Transparent Input or Output Latch t Input Register Setup Time SIR t Input Register Hold Time HIR t Input Register Clock to Combinatorial Output ICO External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) MACH435Q-20 (Com’l) -20 Min Max Unit D-type 10 ns T-type LOW ...
Page 16
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 16 D-type T-type LOW HIGH MACH435Q-20 (Com’l) -20 Min Max Unit ...
Page 17
... mA 5.0 V, OUT CC f=25 MHz (Note 5) A Test Conditions MHz OUT and I (or I and OZL IH OZH MACH435Q-25 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 115 Typ = Characteristics” Chart towards the ...
Page 18
... Input Register Clock to Combinatorial Output 18 D-type T-type LOW HIGH D-type 1/( COA T-type D-type ) CNTA T-type 1/( WLA WHA D-type T-type LOW HIGH D-type 1/( COS T-type D-type ) CNTS T-type 1/( MACH435Q-25 (Com’l) -25 Min Max Unit 21.7 MHz 21.3 MHz 24.4 MHz 23.8 MHz 26.3 MHz ...
Page 19
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. D-type T-type LOW HIGH 1/( WICL WICH MACH435Q-25 (Com’l) -25 Min Max Unit ...
Page 20
... TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS –1 (mA –0.8 –0.6 –0.4 –0 –20 –40 –60 –80 Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH435-12/15/20, Q-20/ 1.0 17469E (V) OH 17469E 17469E-6 ...
Page 21
... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH435Q Frequency (MHz) MACH435-12/15/20, Q-20/25 MACH435 17469E-7 21 ...
Page 22
... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 22 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH435-12/15/20, Q-20/25 Typ PLCC Unit 5 C/W 20 ...
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... V T Out 17469E-9 Gate t WL 17469E- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 17469E-13 MACH435-12/15/20, Q-20/ 17469E PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS V T Input Register to Output Register Setup ...
Page 24
... Latch Gate t IGS Output Latch Gate Notes 1 Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH435-12/15/20, Q-20/ IGO V T 17469E-15 t PDLL SLL V T 17469E-16 ...
Page 25
... Input rise and fall times 2 ns–4 ns typical. Input V Latch T Gate t WICL 17469E-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 17469E- Outputs + V OL Output Disable/Enable MACH435-12/15/20, Q-20/25 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 17469E- 17469E- APR V T 17469E-20 25 ...
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... Don’t Care, Any Change Permitted Does Not Apply Output Commercial 300 390 5 pF MACH435-12/15/20, Q-20/25 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 17469E-22 Measured R Output Value 2 1 ...
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... Min Pattern Data Retention Time Max Reprogramming Cycles 28 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min 10 20 100 MACH435-12/15/20, Q-20/25 Units Test Conditions Years Max Storage Temperature Years Max Operating Temperature Cycles Normal Programming Conditions ...
Page 28
... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH435-12/15/20, Q-20/25 CC 100 17469E-24 29 ...
Page 29
... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH435-12/15/20, Q-20/25 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC 17469E-25 ...
Page 30
... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH435-12/15/20, Q-20/25 Preloaded HIGH Preloaded HIGH 17469E-26 17469E-27 31 ...