MACH4 Lattice, MACH4 Datasheet

MACH4

Manufacturer Part Number

MACH4

Description

High Performance E 2 CMOS In-System Programmable Logic

Manufacturer

Lattice

Datasheet

1.MACH4.pdf (46 pages)

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FEATURES

Publication# 17466

Amendment/0

High-performance, E

Flexible architecture for rapid logic designs

— Excellent First-Time-Fit

— SpeedLocking

— Central, input and output switch matrices for 100% routability and 100% pin-out retention

High speed

— 7.5ns t

— 111.1MHz f

32 to 256 macrocells; 32 to 384 registers

44 to 256 pins in PLCC, PQFP, TQFP and BGA packages

Flexible architecture for a wide range of design styles

— D/T registers and latches

— Synchronous or asynchronous mode

— Dedicated input registers

— Programmable polarity

— Reset/ preset swapping

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— JTAG (IEEE 1149.1) compliant for boundary scan testing

— 3.3-V & 5-V JTAG in-system programming

— PCI compliant (-7/-10/-12 speed grades)

— Safe for mixed supply voltage system designs

— Bus-Friendly

— Programmable security bit

— Individual output slew rate control

Advanced E

Supported by ispDesignEXPERT

— Supports HDL design methodologies with results optimized for MACH 4

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice and third-party hardware programming support

— LatticePRO

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

equipment

and System General

Rev: M

Issue Date: March 2000

Commercial and 10ns t

CMOS process provides high-performance, cost-effective solutions

CNT

software for in-system programmability support on PCs and automated test

inputs and I/Os

performance for guaranteed ﬁxed timing

CMOS 3.3-V & 5-V CPLD families

and reﬁt feature

MACH 4 CPLD Family

High Performance E

In-System Programmable Logic

software for rapid logic development

Industrial

CMOS

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