MACH4 Lattice, MACH4 Datasheet - Page 33

• Manufacturer Part Number: MACH4
• Description: High Performance E 2 CMOS In-System Programmable Logic
• Manufacturer: Lattice

MACH 4 TIMING PARAMETERS OVER OPERATING RANGES
Input Latch Delays with ZHT Option:
t
t
t
Output Delays:
t
t
t
t
Power Delay:
t
Reset and Preset Delays:
t
t
t
t
Clock/LE Width:
t
t
t
t
t
t
t
t
t
SILZ
HILZ
PDILZi
BUF
SLW
EA
ER
PL
SRi
SR
SRR
SRW
WLS
WHS
WLA
WHA
GWS
GWA
WIRL
WIRH
WIL
Input latch setup time - ZHT
Input latch hold time - ZHT
Transparent input latch to internal feedback - ZHT
Output buffer delay
Slow slew rate delay adder
Output enable time
Output disable time
Power-down mode delay adder
Asynchronous reset or preset to internal register output
Asynchronous reset or preset to register output
Asynchronous reset and preset register recovery time
Asynchronous reset or preset width
Global clock width low
Global clock width high
Product term clock width low
Product term clock width high
Global gate width low (for low transparent) or high
(for high transparent)
Product term gate width low (for low transparent) or
high (for high transparent)
Input register clock width low
Input register clock width high
Input latch gate width
Min
10.0
6.0
0.0
8.0
3.0
3.0
4.0
4.0
5.0
4.0
4.5
4.5
5.0
MACH 4 Family
-7
Max
10.0
12.0
6.0
2.0
2.5
9.5
9.5
2.5
10.0
Min
6.0
0.0
8.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
-10
Max Min Max Min Max Min Max Min Max
10.0
10.0
12.0
14.0
6.0
2.0
2.5
2.5
10.0
12.0
6.0
0.0
6.0
6.0
8.0
8.0
6.0
6.0
6.0
6.0
6.0
-12
12.0
12.0
14.0
16.0
6.0
2.0
2.5
2.5
6.0
15.0
15.0
6.0
0.0
6.0
6.0
9.0
9.0
6.0
9.0
6.0
6.0
-14
15.0
15.0
18.0
20.0
6.0
2.0
2.5
2.5
1
(CONTINUED)
15.0
15.0
6.0
0.0
6.0
6.0
9.0
9.0
6.0
9.0
6.0
6.0
6.0
-15
15.0
15.0
18.0
20.0
6.0
2.0
2.5
2.5
17.0
17.0
10.0
10.0
11.0
7.0
6.0
0.0
7.0
7.0
7.0
7.0
7.0
-18
17.0
17.0
20.0
22.0
6.0
2.0
2.5
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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