MACHLV210-12 Lattice, MACHLV210-12 Datasheet
MACHLV210-12
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MACHLV210-12 Summary of contents
Page 1
... FINAL MACHLV210-12/15/20 High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS Low-voltage operation, 3.3-V JEDEC compatible — VCC = +3 +3.6 V < standby current Patented design allows minimal standby current without speed degradation Exclusively designed for 3.3-V applications 44 Pins 64 Macrocells 12 ns tPD Commercial 18 ns tPD Industrial ...
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... I/O Cells 8 8 Macrocells AND Logic Array and Logic Allocator 22 Switch Matrix AND Logic Array and Logic Allocator OE Macrocells I/O Cells 8 I/O –I MACHLV210-12/15/20 I – – Macrocells Macrocells 8 CLK / CLK / 17908D-1 ...
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... CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC PLCC MACHLV210-12/15/ I CLK GND 17908D-2 3 ...
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... Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACHLV210-12/15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) PACKAGE TYPE ...
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... Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACHLV210-18/24 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) PACKAGE TYPE ...
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... The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin three-state output for use in driving a bus. MACHLV210-12/15/20 Available Buried Clusters ...
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... The MACHLV210 is not designed to interface between 3.3-V and 5.0-V logic. Latch-up may occur if VOH for the MACHLV210 is greater than VIH for the 5.0-V device. Although this scenario is unlikely, interfacing the MACHLV210 with 5.0-V devices is not encouraged without necessary latch-up design precautions. MACHLV210-12/15/20 7 ...
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... Switch Matrix Figure 1. MACHLV210 PAL Block MACHLV210-12/15/20 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output M Macro 0 cell 2 Buried Macro M cell 1 2 I/O Cell Output M Macro 2 cell 2 Buried M ...
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... 0 Max (Note 3) OUT 3 MHz CC A (Note MHz and I (or I and OZL IH OZH MACHLV210-12 (Com’l) ) Operating + with +3 +3.6 V Min Typ Max 2.4 0.4 2.0 0.8 10 –10 10 –10 –30 –160 2 60 Unit ...
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... Test Conditions MHz CC A D-type T-type LOW HIGH D-type T-type D-type ) CNT T-type ) CNT D-type T-type LOW HIGH + t ) WICL WICH MACHLV210-12 (Com’l) Typ Unit -12 Min Max Unit 58.8 MHz 55 ...
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... EA t Input, I/O, or Feedback to Output Disable ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACHLV210-12 (Com’l) -12 Min Max Unit ...
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... (Note 0 Max (Note 3) OUT 3 (Note 4) and I (or I and OZL IH OZH MACHLV210-15/20 (Com’l) ) Operating + with +3 +3.6 V Min Typ Max 2.4 0.4 2.0 0.8 10 –10 10 –10 –30 –160 MHz MHz ...
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... MHz CC A D-type T-type LOW HIGH D-type 1/( T-type D-type ) CNT T-type 1/( D-type T-type LOW HIGH 1/( WICL WICH MACHLV210-15/20 (Com’l) Typ Unit -15 -20 Min Max Min Max Unit ...
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... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 16 outputs switching. 14 MACHLV210-15/20 (Com’l) -15 -20 Min Max Min ...
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... (Note 0 Max (Note 3) OUT 3 (Note 4) and I (or I and OZL IH OZH MACHLV210-18/24 (Ind) ) Operating – + with +3 +3.6 V Min Typ Max 2.4 0.4 2.0 0.8 10 –10 10 –10 –30 –160 MHz MHz 60 Unit ...
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... MHz CC A D-type T-type LOW HIGH D-type 1/( T-type D-type ) CNT T-type 1/( D-type T-type LOW HIGH 1/( WICL WICH MACHLV210-18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 13 14 8.5 ns 7.5 ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit at the back of this Data Sheet for test conditions. 3. Parameters measured with 16 outputs switching. MACHLV210-18/24 (Ind) -18 -24 Min ...
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... Permitted Does Not Apply 3 Output Commercial 1 MACHLV210-12/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 17908D-4 Measured ...
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... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACHLV210-12/15/ 1.0 17908D (V) OH 17908D 17908D-7 19 ...
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... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACHLV210-12/15/20 MACHLV210 60 70 17908D-8 ...
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... As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions >50 k ESD Program/Verify Protection Circuitry Input V CC >50 k Preload Feedback Circuitry Input Output MACHLV210-12/15/20 Min Unit 10 Years 20 Years 100 Cycles V CC 17908D-9 21 ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 22 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACHLV210-12/15/20 Typ PLCC Units 15 C/W 40 ...
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... Gate t WL 17908D- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 17908D-15 MACHLV210-12/15/ 17908D- PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS ...
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... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACHLV210-12/15/ IGO V T 17908D-17 t PDLL SLL V ...
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... Gate t WICL 17908D-19 Input, I/ Feedback Registered V T Output t ARR Clock V T 17908D- Outputs + V OL Output Disable/Enable MACHLV210-12/15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 17908D- 17908D- APR ...
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... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACHLV210-12/15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- ...
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... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACHLV210-12/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...
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... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACHLV210-12/15/20 Preloaded HIGH Preloaded HIGH 17908D-26 17908D-27 ...
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... REF .032 TOP VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. .062 .083 .042 .056 .009 .015 .090 .120 .165 .180 SIDE VIEW MACHLV210-12/15/20 .500 .590 REF .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 DA78 6-28- ...