IDT70V05 Integrated Device Technology, IDT70V05 Datasheet - Page 11

• Manufacturer Part Number: IDT70V05
• Description: High-speed 3.3v 8k X 8 Dual-port Static Ram
• Manufacturer: Integrated Device Technology

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
9. To access RAM, CE = V
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
CE
ADDRESS
CE
ADDRESS
bus for the required t
WR
DATA
DATA
DATA
or
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
or
SEM
SEM
R/W
R/W
OUT
OE
IN
IN
(9)
(9)
DW
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
IL
and SEM = V
t
AS
EW
t
(6)
AS
or t
IN
(6)
WP
. To access Semaphore, CE = V
) of a LOW CE and a LOW R/W for memory array writing cycle.
(4)
t
WZ
t
(7)
t
AW
AW
t
t
WC
WC
t
EW
t
WP
IH
(2)
and SEM = V
(2)
6.42
11
t
IL
DW
t
WP
DW
. t
EW
or (t
must be met for either condition.
WZ
+ t
t
WR
DW
) to allow the I/O drivers to turn off and data to be placed on the
Industrial and Commercial Temperature Ranges
(3)
t
DH
t
t
DH
WR
t
OW
(3)
t
HZ
(7)
(4)
(1,3,5,8)
(1,3,5,8)
2941 drw 09
2941 drw 08
WP
.