IDT70V05 Integrated Device Technology, IDT70V05 Datasheet - Page 15

• Manufacturer Part Number: IDT70V05
• Description: High-speed 3.3v 8k X 8 Dual-port Static Ram
• Manufacturer: Integrated Device Technology

Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on port “B” Blocking R/W
3. t
Waveform of BUSY Arbitration Controlled by CE Timing
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If t
ADDR
ADDR
ADDR
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
BUSY
BUSY
WH
WB
and
CE
CE
APS
must be met for both BUSY input (slave) and output (master).
is only for the slave version.
"A"
"B"
"B"
is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
"A"
"B"
"A"
"B"
"B"
(1)
(M/S = V
BUSY
t
APS
R/W
R/W
(2)
IH
"A"
"B"
"B"
)
t
“B”
APS
, until BUSY
(2)
t
BAA
ADDRESS "N"
MATCHING ADDRESS "N"
“B”
goes HIGH.
t
WB
t
BAC
(3)
ADDRESSES MATCH
6.42
t
15
WP
(2)
Industrial and Commercial Temperature Ranges
t
t
BDA
BDC
t
WH
(1)
2941 drw 13
(1)
(M/S = V
IH
2941 drw 15
2941 drw 14
)