IDT70V05 Integrated Device Technology, IDT70V05 Datasheet - Page 19

• Manufacturer Part Number: IDT70V05
• Description: High-speed 3.3v 8k X 8 Dual-port Static Ram
• Manufacturer: Integrated Device Technology

Functional Description
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V05 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
box or message center) is assigned to each port. The left port interrupt
flag (INT
(HEX). The left port clears the interrupt by reading address location
1FFE. Likewise, the right port interrupt flag (INT
port writes to memory location 1FFF (HEX) and to clear the interrupt
flag (INT
message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used
as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
Busy Logic
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
The IDT70V05 provides two ports with separate control, address
If the user chooses the interrupt function, a memory location (mail
Busy Logic provides a hardware indication that both ports of the
The use of BUSY logic is not required or desirable for all applica-
L
R
) is set when the right port writes to memory location 1FFE
), the right port must read the memory location 1FFF. The
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.
BUSY (L)
R
MASTER
Dual Port
SRAM
BUSY (L) BUSY (R)
MASTER
Dual Port
SRAM
BUSY (L) BUSY (R)
) is set when the left
CE
CE
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push-pull type outputs and do not require pull up resistors to
operate. If these SRAMs are being expanded in depth, then the
BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V05 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = V
as a slave (M/S pin = V
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-
Port SRAM to claim a privilege over the other processor for functions
defined by the system designer’s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAM or any other shared
resource.
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
The BUSY outputs on the IDT 70V05 SRAM in master mode, are
When expanding an IDT70V05 SRAM array in width while using
If two or more master parts were used when expanding in width, a
The BUSY arbitration, on a master, is based on the chip enable and
The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with
The Dual-Port SRAM features a fast access time, and both ports are
CE
CE
Industrial and Commercial Temperature Ranges
IH
), and the BUSY pin is an input if the part used
IL
) as shown in Figure 3.
BUSY (R)
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