SI3460 Silicon Laboratories, SI3460 Datasheet - Page 12

• Manufacturer Part Number: SI3460
• Description: IEEE 802.3af PSE INTERFACE AND DC-DC CONTROLLER
• Manufacturer: Silicon Laboratories

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Si3460
After powerup, the STATUS pin drives the base of a PNP transistor that controls an LED. To maintain an accurate
voltage level at the transistor base, it is recommended that the parallel resistance setting the pin voltage be less
than 1 kΩ.
5.3. Operating Mode Sequencing
5.3.1. Detection
After powerup and passing the UVLO threshold voltage of 10 V, the Si3460 enters into the detection state, with
FET M2 off and the dc-dc converter disabled so as to generate no output. Prior to turning on the PSE output FET
M2 and enabling the 250 kHz square wave for the dc-dc converter, a valid detection sequence must take place.
According to the IEEE specifications, the detection process consists of sensing a nominal 25 kΩ signature
resistance in parallel with up to 0.15 µF of capacitance. To eliminate the possibility of false detection events, the
Si3460-EVB reference design performs a robust 3-point detection sequence by varying the voltage across the
sense bridge R1, R2, and R3. The fourth leg of the sense bridge is the load that connects to the drain of M2 and
returns to V
At the beginning of the detection sequence, V
impedance, V
signature resistance is in the RGOOD range of 19 to 26.5 kΩ, the Si3460 proceeds to classification and powerup.
If the PD resistance is not in this range, the detection sequence repeats continuously.
Detection is sequenced approximately every 320 msec and repeats until RGOOD is sensed, indicating a valid PD
has been detected. The STATUS LED (D13) is flashed at the 320 ms rate in synchronization with the detection
process to indicate the PSE is searching for a valid PD.
5.3.2. Classification
After a valid PD is detected, the pass transistor, M2, and the PWM controller are turned on and programmed for an
output voltage of 18 V with a current limit of 75 mA. The current measured during the classification process
determines the class level of the PD. If the class level of the PD is not within the supported level as set by the initial
voltage on the Si3460's STATUS pin (refer to the Operating Mode Configuration section above), an error is
declared and the LED blinks rapidly. If the class level is in the supported range, the Si3460 proceeds to powerup.
Classification level is determined according to the current at ISENSE as shown in Table 9.
If the classification level is at a greater power than can be supported based on R28 and R30, an error condition is
reported by flashing the LED at a 10 Hz rate for two seconds before the state machine goes back to the detection
cycle.
5.3.3. DC-DC Converter Ramp-Up
After the optional classification sequence, the dc-dc converter is powered up to –50 V with a current limit
corresponding to 430 mA. After powerup, power is applied to V
disconnect, or input undervoltage (UVLO) condition. The STATUS LED is continuously lit when power is applied. If
the output power exceeds the level determined by the initial voltage of the STATUS pin, the Si3460 will declare an
error and shut down the port, flashing the LED rapidly to indicate the error (for either two seconds or until reset as
determined by the initial voltage on the STATUS pin).
12
ISENSE Current (Nominal)
6.5mA to 14.5 mA
14.5 mA to 23 mA
EE
OUT
< 6.5 mA
via D8 and L1.
> 23 mA
is then varied from 4.5 to 7.5 V and then back to 4.5 V for 20 ms at each level. If the PD's
Table 9. Classification Levels
Classification Level
Preliminary Rev. 0.4
OUT
Class 3 or 4
is at zero output voltage for 250 ms. With a 10 kΩ source
Class 0
Class 1
Class 2
OUT
as long as there is not an overcurrent fault,
Minimum Power Level
15.4 W
15.4 W
4 W
7 W
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