SI3460 Silicon Laboratories, SI3460 Datasheet - Page 13

• Manufacturer Part Number: SI3460
• Description: IEEE 802.3af PSE INTERFACE AND DC-DC CONTROLLER
• Manufacturer: Silicon Laboratories

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Si3460
5.3.4. DC-DC Converter Soft Start
The PWM control loop of the dc-dc converter is designed to produce a gradual rise in output voltage to eliminate
any inrush current issues. The nominal set point of the dc-dc converter is –50 V. V
at –50 V results in 0.930 V
OUT
at the VSENSE pin. It is possible for there to be almost no load on the dc-dc converter; so, the duty cycle is ramped
slowly up to the dc set point. The duty cycle is initially set to zero (dc-dc converter off). Once the desired voltage set
point is reached, the feedback path from VSENSE is enabled, and the converter is allowed to regulate at the
desired set point.
5.3.5. Disconnect
The Si3460 implements a robust disconnect algorithm. If the output current level drops below 7.5 mA (nominal) for
more than 350 msec, the Si3460 will declare a PD disconnect, and the dc-dc converter clock (250 kHz) and FET
M1 will be turned off. As set by the initial voltage on the STATUS pin, the Si3460 will then automatically resume the
detection process after 250 ms for "Endpoint mode" and two seconds for "Midspan mode." The difference in these
two backoff timings is specified by the IEE 802.3af standard for the midspan and endpoint operating modes.
5.3.6. Current Limit Control
The Si3460's overcurrent trip point is set to 340 mA (nominal), corresponding to 17 W of output power for a
nominal V
voltage of –50 V. If the output current exceeds 340 mA, a timer counts up towards a time-out of
OUT
60 ms. If the current drops below 340 mA, the timer counts down towards zero at 1/16th the rate. If the timer
reaches 60 msec, an overcurrent fault is declared, and the channel is shut down by turning off the dc-dc converter
clock and then turning off FET M1. After an overcurrent fault event, the LED is flashed rapidly. As set by the initial
voltage on the STATUS pin at power-up, the Si3460 will then either automatically resume the detection process
(restart on fault or overload mode) or wait until RST is asserted (restart on reset) before the detect process
resumes.
5.3.7. UVLO
The Si3460-EVB reference design is optimized for 12 to 15 V nominal input voltages (11 V min to 16 V maximum).
If the input voltage drops below 10 V in detection mode or if the output voltage drops below 10 V in classification or
powerup mode, a UVLO condition is declared, which generates the error condition (LED flashing rapidly). An
undervoltage event is a fault condition reported through the status LED as a rapid blinking of 10 flashes per
second. The UVLO condition is continuously monitored in all operating states.
5.3.8. Status LED Function
During the normal detection sequence, the STATUS LED flashes approximately three times per second as the
detection process continues. After successful powerup, the LED glows continuously. If there is an error condition
(i.e. class level is beyond programmed value or a fault or overcurrent condition has been detected), the LED
flashes rapidly 10 times per second). This occurs for two seconds for normal error delay and will continue until
reset if this operational mode is set.
If the Powered Device (PD) is disconnected so that a disconnect event occurs, the LED will start flashing three
times per second once the detect process resumes.
Preliminary Rev. 0.4
13
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