74AC138 Fairchild Semiconductor, 74AC138 Datasheet
74AC138
Manufacturer Part Number
74AC138
Description
1-of-8 Decoder/Demultiplexer
Manufacturer
Fairchild Semiconductor
Datasheet
1.74AC138.pdf
(9 pages)
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DESCRIPTION
The AC138 is an advanced high-speed CMOS 3
TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
If the device is enabled, 3 binary select inputs (A,
B and C) determine which one of the outputs will
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
HIGH SPEED: t
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
CC
PLH
OH
NIH
CC
= 8 A (MAX.) at T
| = I
(OPR) = 2V to 6V
= V
t
PHL
OL
NIL
= 24 mA (MIN)
= 28% V
2
MOS technology.
PD
=4.5 ns (TYP.) at V
CC
A
(MIN.)
= 25
o
C
3 TO 8 LINE DECODER (INVERTING)
CC
= 5V
go low. If enable input G1 is held low or either
G2A or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
(Plastic Package)
B
ORDER CODES :
74AC138B
(Micro Package)
74AC138
M
1/9
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