20T202DA1J Pacer Components, 20T202DA1J Datasheet
20T202DA1J
Related parts for 20T202DA1J
20T202DA1J Summary of contents
Page 1
... CYC - t (/RD) =166ns 200ns CYC - t (/RD) =70ns 100ns WH - Topr: (-20 ~ +75) (- Tstg: (-40 ~ +85) (-50 ~ +85 :100ms(Min.) 1ms(Min.) OFF - t :1ms(Max.) 1us(Min.) r SSVD) Page - Rev. 3.0 Model No.: 20T202DA1J Remark All Pages Page - 5 Page - 4 Page - 5 Page - 7 Page - 8 Page - 2 Page - 3 Page - 17 All Pages Customer’s Approval ...
Page 2
... Set CG-RAM Address. 6.2.8 Set DD-RAM Address. 6.2.9 Read Busy Flag and Address. 6.2.10 Write Data DD-RAM. 6.2.11 Read Data from CG or DD-RAM.................................................................................................... Page - 16 6.3 Example of Initialization after Power ON * Character Code Table (CG-RAM & CG-ROM). 20T202DA1J (Rev. 3.0) ......................................................................... ................................................................................ ................................................................................... .............................................................................. .............................................................................. .............................................................................................................. ...................................................................................... ...
Page 3
... LCD Compatible VFD Module 1. SCOPE * This specification applies to VFD module (Model No.: 20T202DA1J) manufactured by Samsung SDI or SSVD (Shanghai Samsung Vacuum Devices). 2. FEATURES * LCD Compatible: Drop-in-replacement (Same Interface and Mechanical Dimension as LCD Module). * High Quality, Attractive and Readable Display: 5*7 Dot Matrix Type Vacuum Fluorescent Display. ...
Page 4
... Input Current (V "L" level Input Current (V Luminance *1) The in-rush current can be approx. 5 times the specified supply current at power on. *2) A 10k-ohm resistor is pulled-up on each input signals for TTL compatibility. 20T202DA1J (Rev. 3. Dot Matrix with Cursor 40 (20 Digits * 2 Lines) Symbol ...
Page 5
... Note-2: Internal Reset Timing Interval 4.7.2 M68 type CPU Bus Interface Timing t (RS,/R/W) SU 20ns/Min. R DB0~DB7 R/W t (RS,/R/W) SU 20ns/Min DB0~DB7 20T202DA1J (Rev. 3.0) t (VCC) r 1us/Min. t (*) WAIT 100us/Min. Fig.-1. Power-on Reset and /RST Signal Timing t H 10ns/Min. t (E) CYC 500ns/Min. t (E) WH 230ns/Min. ...
Page 6
... Input 5 R/W (/WR) Input 6 E (/RD) Input 7 DB0 8 DB1 9 DB2 10 DB3 I/O 11 DB4 12 DB5 13 DB6 14 DB7 20T202DA1J (Rev. 3.0) t (/WR) CYC 200ns/Min. 10ns/Min. t (/WR) WL 30ns/Min. t (DATA) t (DATA 30ns/Min. 10ns/Min. Valid Data Input Fig.-4. Data Write-in Timing for i80 Interface Mode t (/WR) CYC 200ns/Min. 10ns/Min. ...
Page 7
... R JP1 /RST #3 Jumper Switch for External Reset Rup*8 (10kOhm) DB0~DB7 8 #7~ GND #1 4.10 Through-hole Location for Connector Assembly 20T202DA1J (Rev. 3.0) 72 VDD1 A1~A72 20 G1~G20 E(/RD) R/W(/WR) VFD RS Controller /RST VSS MPU Jumper Switch to Select Interfacing Mode D0~D7 VDD2 DC/DC Converter Fig.-6 System Block Diagram #14 #13 Soldering Hole Diameter: 1 ...
Page 8
... LCD Compatible VFD Module 4.11 Outer Dimensions 4.12 Pattern Details 20T202DA1J (Rev. 3.0) Fig.-8 Drawings for Outer Dimensions Fig.-9 Drawings for Pattern Details Page - Unit: mm Tolerance unless otherwise specified: * Mounting Hole Size: +/- 0.3 * Length: Range < 10: +/- 0.5 Range > 10: +/- 1.0 ...
Page 9
... RAM (lower 5 bits only). Character codes from 00H to 07H (or 08H to 0FH) are assigned to the user-definable characters (refer to Appendix-1 for Character Font Tables). The table on next page shows the relationship between the character codes, CG-RAM addresses, and CG-RAM data for each user-definable character. 20T202DA1J (Rev. 3.0) i80 /WR ...
Page 10
... CG-RAM character patterns are selected when character code bits are all 0. However, since character code bit 3 has no effect, the “A” display example above can be selected by either character code 00H or 08H. 6) ” 1” for CG-RAM data corresponds to display selection and ” 0” to non-selection. 20T202DA1J (Rev. 3.0) CG-RAM Address CG-RAM Data Hex ...
Page 11
... When the user want to RESET the module without turning off the power supply, input both "RST" and "Add" bit high level while giving low level to the others. Please refer to "Fig.-3 CLK and Reset Command Write-in Detail" for particular information about software reset. The reset function will be the same as the power-on reset. 20T202DA1J (Rev. 3. ...
Page 12
... Data RAM * Display Shift Enabled * CG-RAM: Character * Cursor Shift Enabled Generator RAM * ACG: CG-RAM * S Display Shift Address * S Cursor Move * ADD: DD-RAM Address * R Shift to the Right * ACC: Address Counter * R Shift to the Left 20T202DA1J (Rev. 3.0) Instruction Code ...
Page 13
... After writing the DD-RAM data 0 0 Cursor moves one character to the left 1 0 Cursor moves one character to the right 0 1 Display shifts one character to the right without cursor 1 1 Display shifts one character to the left without cursor 20T202DA1J (Rev. 3. ...
Page 14
... Select 2 line display (Using anode output A1 to A80 Select 1 line display (Using anode output A1 to A40. A41 to A80 fixed Low level). BR1, BR0 flag controls the brightness of VFD by modulating pulse width of Anode output as follows. * BR0, BR1 = (0, 0): Brightness = 100%, (0, 1): Brightness = 75%, (1, 0): Brightness = 50%, 20T202DA1J (Rev. 3. ...
Page 15
... CG-RAM or DD-RAM address setting. After a write, the address is automatically increased or decreased by 1 according to the entry mode. The entry mode also determines the display shift. When data is written to the CG-RAM (UDF character data), the D7, D6 and D5 bits are not displayed as characters. 20T202DA1J (Rev. 3. ...
Page 16
... Note) “Dn” is the binary data to be written-in. Power ON Function Set Display ON/OFF 20T202DA1J (Rev. 3.0) Wait for 100 us after Power ON Function set: - Data length: 8 bits Display line No.: 2 lines - Brightness: 100 ...
Page 17
... CG-RAM . (# CG-RAM . . (# CG-RAM . . (# 20T202DA1J (Rev. 3. ...