MC54HC163A Motorola, MC54HC163A Datasheet - Page 4

• Manufacturer Part Number: MC54HC163A
• Description: (MC54HC161A / MC54HC163A) Presettable Counters
• Manufacturer: Motorola

MOTOROLA
counters that feature parallel Load, synchronous or asynchro-
nous Reset, a Carry Output for cascading and count–enable
controls.
asynchronous Reset and synchronous Reset, respectively.
INPUTS
Clock (Pin 2)
vances with the rising edge of the Clock input. In addition, con-
trol functions, such as resetting and loading occur with the
rising edge of the Clock input. In addition, control functions,
such as resetting (HCT163A) and loading occur with the rising
edge of the Clock Input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
on these pins may be synchronously loaded into the internal
flip–flops and appear at the counter outputs. P0 (Pin 3) is the
least–significant bit and P3 (Pin 6) is the most–significant bit.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
nificant bit and Q3 (Pin 11) is the most–significant bit.
Ripple Carry Out (Pin 15)
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count state.
The logic equation for this output is:
MC54/74HCT161A MC54/74HCT163A
The HCT161A/163A are programmable 4–bit synchronous
The HCT161A and HCT163A are binary counters with
The internal flip–flops toggle and the output count ad-
These are the data inputs for programmable counting. Data
These are the counter outputs. Q0 (Pin 14) is the least–sig-
When the counter is in its maximum state 1111, this output
Ripple Carry Out = Enable T Q0 Q1 Q2 Q3
15
14
13
12
0
FUNCTION DESCRIPTION
OUTPUT STATE DIAGRAM
Binary Counters
11
1
10
2
4
CONTROL FUNCTIONS
Resetting
flops and sets the outputs (Q0 through Q3) to a low level. The
HCT161A resets asynchronously, and the HCT163A resets
with the rising edge of the Clock input (synchronous reset).
Loading
9) loads the data from the Preset Data input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
Count Enable/Disable
P (Pin 7) and Enable T (Pin 10). The devices count when these
two pins and the Load pin are high. The logic equation is:
according to Table 1. In general, Enable P is a count–enable
control: Enable T is both a count–enable and a Ripple–Carry
Output control.
Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.
Load
A low level on the Reset pin (pin 1) resets the internal flip–
With the rising edge of the Clock, a low level on Load (pin
These devices have two count–enable control pins: Enable
The count is either enabled or disabled by the control inputs
H
X
X
L
3
9
Control Inputs
Count Enable = Enable P Enable T Load
Enable
4
5
6
7
8
P
H
H
X
L
Table 1. Count Enable/Disable
Enable
H
H
H
T
L
No Count
No Count
No Count
Q0–Q3
Count
High–Speed CMOS Logic Data
Result at Outputs
High when Q0–Q3
High when Q0–Q3
Ripple Carry Out
are maximum*
are maximum*
DL129 — Rev 6
L