MC705P6A Motorola, MC705P6A Datasheet - Page 41

• Manufacturer Part Number: MC705P6A
• Description: Microcontrollers
• Manufacturer: Motorola

Chapter 7
Serial Input/Output Port (SIOP)
7.1 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial
communications between peripheral devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block
diagram of the SIOP is shown in
is MSB or LSB first.
The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in
register SCR), port B DDR and data registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could affect the transmitted or received
data.
Freescale Semiconductor
7 6 5 4 3 2 1 0
REGISTER
CONTROL
$0A
HCO5 INTERNAL BUS
GENERATOR
CPU CLOCK
INTERNAL
BAUD
RATE
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Figure
Figure 7-1. SIOP Block Diagram
7 6 5 4 3 2 1 0
REGISTER
STATUS
7-1. A mask programmable option determines whether the SIOP
$0B
7 6 5 4 3 2 1 0
REGISTER
SHIFT
8-BIT
$0C
SPE
SDO
SDI
SCK
CONTROL
LOGIC
I/O
SDO/PB5
SDI/PB6
SCK/PB7
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