CY7C4245V-15ASXC Cypress Semiconductor Corp, CY7C4245V-15ASXC Datasheet - Page 11

• Manufacturer Part Number: CY7C4245V-15ASXC
• Description: IC SYNC FIFO MEM 4KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245V-15ASXC

• Access Time: 10ns
• Memory Size: 72K (4K x 18)
• Package / Case: 64-LQFP
• Function: Synchronous
• Data Rate: 67MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 4 K x 18
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1716

Document #: 38-06029 Rev. *C
Switching Waveforms
Read Cycle Timing
Notes:
Reset Timing
15. t
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
REN, WEN,
between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
Q
0
EF,PAE
FF,PAF,
Q
WCLK
RCLK
–Q
WEN
REN
0
–Q
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
OE
EF
17
RS
HF
LD
17
[16]
t
ENS
t
OLZ
(continued)
t
ENH
t
CLKH
t
t
A
REF
t
t
t
RSF
RSF
RSF
t
OE
t
RS
t
CLK
t
SKEW2
NO OPERATION
[15]
t
CLKL
SKEW2
, then EF may not change state until the next RCLK edge.
VALID DATA
t
RSR
t
REF
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
t
OHZ
OE = 1
OE = 0
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[17]
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