CY7C4245V-15ASXC Cypress Semiconductor Corp, CY7C4245V-15ASXC Datasheet - Page 6

• Manufacturer Part Number: CY7C4245V-15ASXC
• Description: IC SYNC FIFO MEM 4KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245V-15ASXC

• Access Time: 10ns
• Memory Size: 72K (4K x 18)
• Package / Case: 64-LQFP
• Function: Synchronous
• Data Rate: 67MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 4 K x 18
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1716

Document #: 38-06029 Rev. *C
Width Expansion Configuration
The CY7C42X5V can be expanded in width to provide word
widths greater than 18 in increments of 18. During width
expansion mode all control line inputs are common and all
flags are available. Empty (Full) flags should be created by
Depth Expansion Configuration (with Program-
mable Flags)
The CY7C42X5V can easily be adapted to applications
requiring more than 64/256/512/1024/2048/4096 words of
buffering. Figure 2 shows Depth Expansion using three
CY7C42X5Vs. Maximum depth is limited only by signal
loading. Follow these steps:
1. The first device must be designated by grounding the First
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must
4. The Read Expansion Out (RXO) pin of each device must
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth
7. EF, FF, PAE, and PAF are created with composite flags by
FULL FLAG (FF)
Load (FL) control input.
be tied to the Write Expansion In (WXI) pin of the next
device.
be tied to the Read Expansion In (RXI) pin of the next
device.
Expansion Configuration.
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
Figure 1. Block Diagram of Low-Voltage Synchronous FIFO Memories Used in a Width Expansion Configuration
PROGRAMMABLE(PAE)
DATA IN (D)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF FULL FLAG (HF)
LOAD (LD)
36
18
FF
RESET (RS)
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
EF
FIRST LOAD (FL)
18
18
ANDing the Empty (Full) flags of every FIFO. This technique
will avoid ready data from the FIFO that is “staggered” by one
clock cycle due to the variations in skew between RCLK and
WCLK. Figure 2 demonstrates a 36-word width by using two
CY7C42X5V.
FF
RESET (RS)
7C4425V
7C4205V
7C4215V
7C4225V
7C4235V
7C4245V
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
EF
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE(OE)
PROGRAMMABLE(PAF)
DATA OUT (Q)
EMPTYFLAG (EF)
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