HT45R34 Holtek Semiconductor, HT45R34 Datasheet - Page 10

• Manufacturer Part Number: HT45R34
• Description: C/R to F Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

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Oscillator Configuration
There are two oscillator circuits in the microcontroller.
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, the choice of which is
determined by a configuration option. When the device
enters the Power-down Mode, the system oscillator will
stop running and will ignore external signals to conserve
power.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required to produce oscillation. The
resistance must range from 24k
clock, divided by 4, is available on OSC2, which can be
used to synchronize external logic. The RC oscillator
provides the most cost effective solution, however, the
frequency of oscillation may vary with VDD, tempera-
tures and the device itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external compo-
nents are required. Instead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors con-
nected between OSC1, OSC2 and ground are required,
if the oscillator frequency is less than 1MHz.
The WDT oscillator is a free running on-chip RC oscilla-
tor which requires no external components. Even if the
system enters the Power Down Mode, where the sys-
tem clock is stopped, the WDT oscillator will continue to
operate with a period of approximately 65 s at 5V. The
WDT oscillator can be disabled by a configuration option
to conserve power.
Watchdog Timer - WDT
The WDT clock can be sourced from its own dedicated
internal oscillator (WDT oscillator), or from the or in-
struction clock, which is the system clock divided by 4.
The choice is determined via a configuration option. The
WDT timer is designed to prevent a software malfunc-
tion or sequence from jumping to an unknown location
with unpredictable results. The Watchdog Timer can be
disabled by a configuration option. If the Watchdog
Rev. 1.20
System Oscillator
to 1M . The system
10
Timer is disabled, any executions related to the WDT re-
sult in no operation.
The WDT clock source is first divided by 256. If the inter-
nal WDT oscillator is used ,this gives a nominal time-out
period of approximately 17ms at 5V. This time-out pe-
riod may vary with temperatures, VDD and process vari-
ations. By using the WDT prescaler, longer time-out
periods can be realised. Writing data to the WS2, WS1,
WS0 bits in the WDTS register, can give different
time-out periods. If WS2, WS1 and WS0 are all equal to
1, the division ratio will be 1:128, and the maximum
time-out period will be 2.1s at 5V. If the internal WDT os-
cillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the Power Down state the WDT will stop
counting and lose its protecting purpose. The high nib-
ble and bit 3 of the WDTS can be used for user defined
flags.
If the device operates in a noisy environment, using the
internal WDT oscillator is the recommended choice,
since the HALT instruction will stop the system clock.
The WDT overflow under normal operation will generate
a chip reset and set the status bit TO . But in the
Power Down mode, the overflow will generate a warm
reset , where only the Program Counter and Stack
Pointer are reset to zero. To clear the contents of the
WDT, including the WDT prescaler, three methods can
be used; an external reset (a low level to RES), a soft-
ware instruction and a HALT instruction. The software
instruction includes CLR WDT instruction and the in-
struction pair
these two types of instruction, only one can be active de-
pending on the configuration option
selection option . If the CLR WDT is selected, i.e.
CLRWDT times equal one, any execution of the CLR
WDT instruction will clear the WDT. In the case that
CLRWDT times equal two, these two instructions must
be executed to clear the WDT; otherwise, the WDT may
reset the chip as a result of a time-out.
CLR WDT1 and CLR WDT2 are chosen, i.e.
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WDTS (09H) Register
CLR WDT1 and CLR WDT2 . Of
WS0
0
1
0
1
0
1
0
1
Division Ratio
October 15, 2007
CLR WDT times
1:128
HT45R34
1:16
1:32
1:64
1:1
1:2
1:4
1:8