HT48R03 Holtek Semiconductor, HT48R03 Datasheet - Page 6

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HT48R03

Manufacturer Part Number
HT48R03
Description
(HT48R01 - HT48R03) 10-Pin MSOP I/O Type 8-Bit OTP MCU
Manufacturer
Holtek Semiconductor
Datasheet
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The program counter controls the sequence in which the
instructions stored in program memory are executed
and its contents specify the full range of program mem-
ory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
Note: *11~*0: Program Counter bits
Rev. 1.00
Initial Reset
External Interrupt
Timer/Event Counter Overflow
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
#11~#0: Instruction code bits
For HT48R01, the Program Counter is 10 bits wide, i.e. from *9~*0
For HT48R02, the Program Counter is 11 bits wide, i.e. from *10~*0
For HT48R03, the Program Counter is 12 bits wide, i.e. from *11~*0
Mode
S11
#11
*11
*11
0
0
0
S10
#10
*10
*10
0
0
0
Program Counter
S9
#9
*9
*9
Execution Flow
0
0
0
S8
#8
*8
*8
0
0
0
6
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
S11~S0: Stack register bits
@7~@0: PCL bits
@7
#7
S7
*7
0
0
0
Program Counter+2
Program Counter
@6
#6
S6
*6
0
0
0
HT48R01/HT48R02/HT48R03
@5
S5
#5
*5
0
0
0
@4
S4
#4
*4
0
0
0
@3
S3
#3
*3
0
0
1
December 20, 2006
@2
S2
#2
*2
0
1
0
@1
S1
#1
*1
0
0
0
@0
S0
#0
*0
0
0
0

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