LM1253AN National Semiconductor, LM1253AN Datasheet

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LM1253AN

Manufacturer Part Number
LM1253AN
Description
Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator
Manufacturer
National Semiconductor
Datasheet
© 2000 National Semiconductor Corporation
LM1253A
Monolithic Triple 180 MHz I
Integrated Analog On Screen Display (OSD) Generator
General Description
The LM1253A pre-amp is an integrated high voltage triple
CRT pre-amp and Analog On Screen Display (OSD) genera-
tor. The IC is I
rameters necessary to setup and adjust the brightness and
contrast in the CRT display. In addition, it provides a pro-
grammable period vertical blanking pulse which is used to
blank the G1.
The LM1253A pre-amp is designed to work in cooperation
with the LM2453 driver, and provides a multiplexed video
signal (VideoPlex) interface to enable the DC clamp levels at
the cathode to be varied in order to set up the CRT bias and
to allow individual adjustment for brightness.
The Analog OSD has a selectable palette allowing a wide se-
lection of colors. The preset level of the OSD can be con-
trolled by I
is internally mixed with the video signal, before the gain sec-
tion, and thus gives excellent white tracking of the OSD with
the white color point setting of the video.
The Brightness settings are also mixed into the video signal
before the gain matching controls and consequently give ex-
cellent white color point tracking with variations in the Bright-
ness control. An active horizontal blanking signal is added to
the video at the output, giving excellent smear performance,
and preventing video content dependent DC bias offsets as
a result of high frequency over shoot.
The OSD horizontal sync and blanking signal is derived from
a positive going flyback pulse. The digital section provides
easy interfacing of this signal with the deflection circuits.
The vertical blanking signal is taken from the vertical sync
signal, and the blanking duration is programmable. This sys-
tem is highly integrated and requires a minimal number of
external components.
Black level clamping of the signal is carried out directly on
the AC coupled input signal into the high impedance pream-
plifier input, thus eliminating the need for additional black
level clamp capacitors.
2
C to suit different CRT displays. The OSD signal
2
C controlled, and allows control of all the pa-
DS101265
2
C CRT Pre-amp With
The outputs are referenced to a DC level produced by the
LM1253A Pre-amp, and so are guaranteed to provide stable
DC operating levels within the system without the need for
additional external feedback components.
The IC is packaged in an industry standard wide body 28-
lead DIL molded plastic package.
Features
n 190 two-color ROM based Character Fonts
n 64 four-color ROM based Character Fonts
n Supports a programmable page size with up to 512
n Support for 2 Display Windows (size of each window is
n Programmable start position for each Display Window
n Programmable Resolutions: from 512 to 960 pixels per
n Programmable Character Height, with automatic height
n Programmable Row Spacing between each display
n Maximum Pixel clock of 92.2 MHz
n I
n Button boxes
n 180 MHz preamplifier with full video signal parametric
n VideoPlex
n OSD mixing with 64 out of 512 color mask
Intended Applications
n 1280 x 1024 Displays up to 75 Hz requiring OSD
characters and line definition codes
configurable)
line in 64 pixel increments
control with mode change
character row
control
programmable selection
capability
2
C compatible interface to controlling micro-controller
interface to the LM2453 driver
www.national.com
May 2000

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LM1253AN Summary of contents

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... Black level clamping of the signal is carried out directly on the AC coupled input signal into the high impedance pream- plifier input, thus eliminating the need for additional black level clamp capacitors. © 2000 National Semiconductor Corporation 2 C CRT Pre-amp With The outputs are referenced level produced by the ...

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Table of Contents Block and Connection Diagrams Absolute Maximum Ratings Operating Ratings Electrical Characteristics Test Circuit Test Settings Pin Descriptions Input/Output Schematics National VideoPlex Video System ESD and Arc-Over Protection Pre-Amp Functional Description Horizontal Phase Locked Loop Fault Operation Power ...

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Block and Connection Diagrams FIGURE 1. Block Diagram 3 DS101265-1 www.national.com ...

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... Block and Connection Diagrams www.national.com (Continued) 28-Lead (0.600’’ wide) Molded Dual-In-Line Package Order Number LM1253AN See NS Package Number N28B FIGURE 2. Connection Diagram 4 DS101265-2 ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Input Voltage Storage Temperature Range STG T JMAX Active Video Signal Electrical Characteristics (See Figure 3 for Test Circuit, and Table 1 for Control Test Settings Chart) ...

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Brightness/Bias Signal Electrical Characteristics (See Figure 3 for Test Circuit, and Table 1 for Control Test Settings Chart) Unless otherwise noted +5V Symbol Parameter V Maximum Blanking Level BLANK MAX V Minimum Blanking Level BLANK MIN ...

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External Interface Signals Electrical Characteristics (See Figure 3 for Test Circuit) Unless otherwise noted +5V Symbol Parameter V V Undervoltage Detection Threshold CCDET CC F Free Run HBLANK Frequency FREE_RUN V Low Level Input Voltage for ...

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Test Settings No. Control of Bits Contrast 7 R,G,B Gain 7 Brightness 8 R,G,B Bias 8 DC Offset 3 Pedestal Offset 3 Pin Descriptions Pin 1 — resistor is connected to this EXT REF ...

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Pin Descriptions (Continued) as the DC clamp control capacitors. A value of 0.0047 µF is used in the demo boards. The schematic shown in Figure 29 which has a series resistance and ground should be used to ...

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Pin Descriptions (Continued) Pin 13 — Clamp A positive going clamp signal is input on this pin. Using this signal black level clamping of the video is carried out directly on the input video that is AC coupled into the ...

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Pin Descriptions (Continued set to limit the input current into the maxi- LIMITH mum value during flyback and −150 µA during nor- mal forward scan. For example flyback with ...

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Pin Descriptions (Continued) VFLYBACK vertical flyback pulse is kept high during that ini- tial period to prevent the output VBLANK from switching be- tween high and low states. Loss of vertical flyback pulse implies that the monitor is not scanning, ...

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Pin Descriptions (Continued) Pin 20 — Digital Supply 5V supply for the OSD section of the LM1253A. Pins 19 and 20 should be tied together under normal operating conditions. Pin 21 — Analog Supply 5V supply for the video section ...

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Input/Output Schematics FIGURE 14. Pins 4, 5, and 6 (Video In) FIGURE 15. Pin 11 (PLL C) FIGURE 16. Pin 12 (ABL) www.national.com (Continued) DS101265-17 DS101265-18 FIGURE 20. Pins 16 and 17 (SDA and SCL) DS101265-19 14 DS101265-20 FIGURE 17. ...

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Input/Output Schematics National VideoPlex Video System The LM1253A CRT Pre-Amp in conjunction with the LM2453 CRT driver uses the National VideoPlex multiplexed video FIGURE 23. National VideoPlex Video Signal (Pre-Amp Output) The response of the LM2453 CRT driver to the ...

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National VideoPlex Video System FIGURE 24. DC I/O Transfer Characteristics for the LM2453 CRT Driver (Test Conditions: V ESD and Arc-Over Protection The LM1253A incorporates full ESD protection with special consideration given to maximizing arc-over robustness. The monitor designer must ...

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ESD and Arc-Over Protection (Continued) FIGURE 26. Recommended Video Input ESD Protection 2 The I C specification recommends that the SDA and SCL pins should be protected from arc-over. This is done by add- ing a resistor in series with ...

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Pre-Amp Functional Description TABLE 2. Registers Controlling the Output Video and Clamp Signal Parameter Address BGAIN 8430h GGAIN 8431h RGAIN 8432h CONTRAST 8433h BBIAS 8434h GBIAS 8435h RBIAS 8436h BRIGHTNESS 8437h PEDESTAL 8438h Bits 7–5 OSD 8438h Bits 4–3 CONTRAST ...

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Pre-Amp Functional Description (Continued) Active Video Transfer Characteristic Gain, contrast, and DC Offset control the amplitude of the active video. The Contrast Control range (10X) and the Gain Control range (3.2X). The DC offset ...

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Schematics FIGURE 29. LM1253A/LM2453 Demo Board Schematic www.national.com 20 DS101265-34 ...

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Schematics (Continued) FIGURE 30. LM1253A/LM2453 Demo Board Schematic (continued) 21 DS101265-69 www.national.com ...

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PCB Layout www.national.com FIGURE 31. LM1253A/LM2453 Demo Board Layout 22 DS101265-35 ...

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OSD Generator Operation Page Operation The block diagram of the OSD generator is shown Figure 32 . FIGURE 32. Block Diagram of the OSD Generator Video information is created using any of the 256 pre- defined characters stored in the ...

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OSD Generator Operation OSD Video Timing The OSD SELECT signal switches the source of video infor- mation within the preamplifier from external video to the in- ternally generated OSD video. Windows Two separate windows can be opened, utilizing the data ...

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OSD Generator Operation Attribute Tables Each character has an attribute value assigned the page RAM. The attribute value is 4 bits wide, making each character entry in the page RAM 12 bits wide in total. The at- ...

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OSD Generator Operation CHAR1 Bit 11 Bit 0 (of Previous Character) CHAR1 RAISED Effect on the screen: FIGURE 37. Shadowing www.national.com (Continued) Bit 0 Bit 11 Bit 0 Line 0 (of Previous Character) CHAR1 Line 17 Line 0 (of Character ...

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... LM1253A for writing is BAh (1011 1010) and the address for reading is BBh (1011 1011). The development software provided by National Semiconductor will automati- cally take care of the difference between the read and write addresses if the target address under the communications tab is set to BAh ...

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Micro-Controller Interface The write sequence consists of the Start Pulse, the Slave Device Address, the Read/Write bit (a zero, indicating a write) and the Acknowledge bit; the next byte is the least sig- nificant byte of the address to be ...

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LM1253A Address Map Address R/W Range CHARACTER ROM 0000h–2FFFh R ROM Character Fonts, 190 two-color Character Fonts that are read-only. The format of the address is as follows: A15–A14: Always zeros. A13–A6: Character value (00h–BFh are valid values) A5–A1: Row ...

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Pre-Amp Interface Registers Register Address Default Fonts-2 Color 0000–2FFE +1 Fonts-4 Color 3000–3FFE +1 Display Page 8000–83FF FRMCTRL1 8400 FRMCTRL2 8401 CHARFONTACC 8402 VBLANKDUR 8403 CHARHTCTRL 8404 BBHLCTRLB0 8405 BBHLCTRLB1 8406 BBLLCTRLB0 8407 BBLLCTRLB1 8408 CHSDWCTRLB0 8409 CHSDWCTRLB1 840A ROMSIGCTRL ...

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Pre-Amp Interface Registers Register Address Default BGAINCTRL 8430 GGAINCTRL 8431 RGAINCTRL 8432 CONTRCTRL 8433 BBIASCTRL 8434 GBIASCTRL 8435 RBIASCTRL 8436 BRIGHTCTRL 8437 DCOFFSET 8438 GLOBALCTRL 8439 PLLFREQRNG 843E SRTSTCTRL 843F Note: Set Reserved bits to 0. Two-Color Attribute Table Register ...

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Four-Color Attribute Table TABLE 8. Four-Color Attribute Registers (Continued) Register Address D7 ATT4C3n +3 X ATT4C4n +4 C3B[1:0] ATT4C5n +5 C4B[0] ATT4C6n +6 X ATT4C7n +7 X Note: Set Reserved bits to 0. Four-color display character Attribute Table. The attributes ...

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Display Page RAM (Continued) Row End Code To signify the end of a row of characters, a special ‘Row-End’ (RE) code is used in place of a character code. Bits 11–4 Row-End Code: A special character code of 01h Bits ...

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Display Page RAM (Continued) The skip-line parameters associated with the next row must always be written to the location immediately after the preceding row’s row-end character. The only exception to this rule is when a window-end character (value 00h) is ...

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Display Page RAM (Continued) Command Sent (hex start condition (See the Micro-Controller Interface Section) Chip address (See the Micro-Controller Interface Section Address LSB 80 Address MSB 00 Use Attribute table 00 for the following characters ...

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Display Page RAM (Continued) Notes: • Every row must begin with an attribute and a SL value. Display Page RAM memory location 8000h will always be associated with the SL of row 0 of Display Window #1. 2 • If ...

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Display Page RAM (Continued) TABLE 10. Example 2 I Command Sent (hex) 01 Use Attribute table 01 for the following characters 03 Skip 3 lines 05 Character “D” 06 Character “E” 07 Character “F” 01 Row end ...

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Display Page RAM (Continued) Notes: • In order to centralize the three characters above the five characters on the row below, a ‘transparent’ blank char- acter has been used as the first character on the row. • In order to ...

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Display Page RAM (Continued) Command Sent (hex start condition (See the Micro-Controller Interface Section) Chip address (See the Micro-Controller Interface Section Address LSB 80 Address MSB 00 Use Attribute table 00 for the following characters ...

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Control Register Definitions OSD INTERFACE REGISTERS 2 Frame Control Register address 8400h). REGISTER NAME: FRMCTRL1 Bit 7 RSV RSV RSV TD CDPR Bit 0: On-Screen Display Enable. The On-Screen Display will be disabled when this bit is ...

Page 41

Control Register Definitions Vertical Blank Duration Control Register (I REGISTER NAME: VBLANKDUR Bit 7 RSV VB6 VB5 VB4 VB3 Bits 6–0: Vertical Blank Duration. These seven bits set the duration of the VBLANK signal in numbers of horizontal scan lines. ...

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Control Register Definitions ROM Signature Control Register (I REGISTER NAME: ROMSIGCTRL Bit 7 RSV RSV RSV RSV RSV Bit 0: Calculate ROM Signature. Setting this bit causes the entire ROM to be read, sequentially, and a 16 bit CRC calculated ...

Page 43

Control Register Definitions Display Window 2 Horizontal Pixel Start Location Register (I REGISTER NAME: HSTRT2 (8418h) Bit 7 2H7 2H6 2H5 2H4 2H3 Bits 7–0: Display Window 2 Horizontal Pixel Start Location. These seven bits determine the starting horizontal pixel ...

Page 44

Control Register Definitions PRE-AMP INTERFACE REGISTERS Blue Channel Gain Control Register (I REGISTER NAME: BGAINCTRL (8430h) Bit 7 RSV BG6 BG5 BG4 BG3 Bits 6–0: Blue Channel Gain Control. These seven bits determine the gain for the Blue Channel. Bit ...

Page 45

Control Register Definitions Red Bias Clamp Pulse Amplitude Control Register (I REGISTER NAME: RBIASCTRL (8436h) Bit 7 RC7 RC6 RC5 RC4 RC3 Bits 7–0: Red Channel Bias Clamp Pulse Amplitude Control. These six bits determine the bias clamp value for ...

Page 46

Control Register Definitions Note: These settings are valid when R28 = 6.2k, C23 = 0.1 µF, C33 = 2.2 nF. Frequency 30 kHz 35 kHz 40 kHz 45 kHz 50 kHz 55 kHz 60 kHz 65 kHz 70 kHz 75 ...

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Control Register Definitions Bits 21–18: Enhanced Feature Bits. The enhanced features are determined as follows: Bits 21–28 0000b 0001b 0010b 0011b 01XXb 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Bits 31–24: Reserved FOUR-COLOR ATTRIBUTE FORMAT REGISTER NAME: ATT4C7n (8507h ...

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Control Register Definitions Bits 21–18 1010b 1011b 1100b 1101b 1110b 1111b Bits 40–32: Color 3. These nine bits indicate the value of the color to be displayed as Color 3. This is displayed when the cor- responding pixel data bit ...

Page 49

Control Register Definitions 2. overwriting the pixels in the top line of the skipped lines below, in the case where skip lines are present below a boxed char- acter. Characters should be designed so that button boxes will not interfere ...

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Control Register Definitions In the LM1253A, an approximation method is used to determine which lines are repeated, and how many times each line is re- peated. The constant character height mechanism will not decrease the OSD character matrix to less ...

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Character Font FIGURE 45. Character Font 00-2F 51 DS101265-62 www.national.com ...

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Character Font (Continued) www.national.com FIGURE 46. Character Font 30-5F 52 DS101265-63 ...

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Character Font (Continued) FIGURE 47. Character Font 60-8F 53 DS101265-64 www.national.com ...

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Character Font (Continued) www.national.com FIGURE 48. Character Font 90-BF 54 DS101265-65 ...

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Character Font (Continued) FIGURE 49. Character Font C0-DF 55 DS101265-66 www.national.com ...

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Character Font (Continued) www.national.com FIGURE 50. Character Font E0-FF 56 DS101265-67 ...

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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted 28-Lead (0.600’’ wide) Molded Dual-In-Line Package Order Number LM1253AN NS Package Number N28B 2. A critical component is any component of a life ...

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