LM1253AN National Semiconductor, LM1253AN Datasheet - Page 40

• Manufacturer Part Number: LM1253AN
• Description: Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator
• Manufacturer: National Semiconductor

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Control Register Definitions
OSD INTERFACE REGISTERS
Frame Control Register 1 (I
REGISTER NAME: FRMCTRL1
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bits 7–4: RESERVED.
Frame Control Register 2 (I
REGISTER NAME: FRMCTRL2
Bits 4–0: Blinking Period. These five bits set the blinking period of the blinking feature, which is determined by multiplying the
Bits 7–5: Pixels per Line. These three bits determine the number of pixels per line.
Character Font Access Control Register (I
REGISTER NAME: CHARFONTACC
Bit 0:
Bit 1:
Bits 7–2: RESERVED.
Bit 7
Bit 7
Bit 7
RSV
RSV
PL2
RSV
RSV
PL1
On-Screen Display Enable. The On-Screen Display will be disabled when this bit is a zero. When this bit is a one the
On-Screen Display will be enabled and Display Window 1 will be enabled if Bit 1 of this register is a one; likewise Dis-
play Window 2 will be enabled if Bit 2 of this register is a one.
Display Window 1 Enable. When Bit 0 of this register and this bit are both ones, Display Window 1 is enabled. If either
bit is a zero, then Display Window 1 will be disabled.
Display Window 2 Enable. When Bit 0 of this register and this bit are both ones, Display Window 2 is enabled. If either
bit is a zero, then Display Window 2 will be disabled.
Clear Display Page RAM. Writing a one to this bit will result in setting all of the Display Page RAM values to zero. This
bit is automatically cleared after the operation is complete.
Transparent Disable. When this bit is a zero, a palette color of black (ie color palette look-up table value of ‘000 000
000’) in the first 8 palette look-up table address locations (i.e., ATT = 0h–7h) will be translated as transparent. When
this bit is a one, the color will be translated as black.
value of these bits by 8, and then multiplying the result by the vertical field rate.
Four-color pixel data value Bit indicator. This bit indicates if Bit 0 (when a zero) or Bit 1 (when a one) of the four-color
pixel data value is being accessed via I
Character/Attribute Code Indicator. This bit controls what value is read via I
dress range 8000h–81FFh). When this bit is a 0, such reads will return the character code. When this bit is a 1, the
attribute code will be returned.
Bits 7–5
RSV
000b
001b
010b
011b
100b
101b
110b
111b
RSV
PL0
RSV
BP4
TD
2
2
C address 8400h).
C address 8401h).
CDPR
RSV
BP3
D2E
RSV
BP2
2
C address 8402h).
D1E
BP1
C/A
2
C addresses 3000h–3FFFh.
512 pixels per line
576 pixels per line
640 pixels per line
704 pixels per line
768 pixels per line
832 pixels per line
896 pixels per line
960 pixels per line
OsE
BP0
Bit 0
Bit 0
Bit 0
Bit
Description
40
2
C reads of the Display Page RAM (ad-
125 kHz
119 kHz
112 kHz
106 kHz
100 kHz
Max Fh
93 kHz
87 kHz
81 kHz