LM1253AN National Semiconductor, LM1253AN Datasheet - Page 31

• Manufacturer Part Number: LM1253AN
• Description: Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator
• Manufacturer: National Semiconductor

ATT2C0n
ATT2C1n
ATT2C2n
ATT2C3n
ATT4C0n
ATT4C1n
ATT4C2n
BGAINCTRL
GGAINCTRL
RGAINCTRL
CONTRCTRL
BBIASCTRL
GBIASCTRL
RBIASCTRL
BRIGHTCTRL
DCOFFSET
GLOBALCTRL
PLLFREQRNG
SRTSTCTRL
Register
Register
Note: Set Reserved bits to 0.
Note: Set Reserved bits to 0.
Pre-Amp Interface Registers
Two-Color Attribute Table
Two-color display character Attribute Table. The attributes for two-color display characters may be written or read via the following
address format:
A15–A6: Always 1000_0100_01b.
A5–A2: Attribute code (0h-Fh are valid values), n
A1–A0: Determines which of the 3 bytes is to be accessed.
NOTE: In the table, n indicates the attribute number 0
NOTE: When writing, bytes 0 through 2 must be written, in that order. Bytes 0 through 2 will take effect after byte 2 is written.
Since byte 3 contains all reserved bits, this byte may be written, but no effect will result.
When reading, it is OK to read only one, two, or all three bytes.
If writing more than one 2-color attributes using the auto increment feature, all four bytes must be written.
Four-Color Attribute Table
Register
Address
Address
8440 +
8500 +
(n*4)
(n*8)
+1
+2
+3
+1
+2
Address
843E
8430
8431
8432
8433
8434
8435
8436
8437
8438
8439
843F
C2B[0]
C2B[0]
D7
D7
X
X
X
C1B[1:0]
C1B[1:0]
Default
60h
60h
60h
60h
80h
80h
80h
80h
94h
00h
16h
00h
TABLE 8. Four-Color Attribute Registers
LM1253A Four-Color Attribute Registers
TABLE 7. Two-Color Attribute Registers
LM1253A Two-Color Attribute Registers
D6
D6
TABLE 6. Pre-Amp Interface Registers
LM1253A Pre-Amp Interface Registers
X
X
X
(Continued)
D7
X
X
X
X
X
X
X
C2G[2:0]
C2G[2:0]
PEDESTAL[2:0]
<
D5
=n
D5
X
<
AID
D6
=15
X
X
31
C1G[2:0]
C1G[2:0]
D4
D4
X
D5
IVIGAIN[1:0]
X
X
EF[3:0]
EF[3:0]
BRIGHTNESS[7:0]
OSD CONT[1:0]
D4
X
X
GBIAS[7:0]
BBIAS[7:0]
RBIAS[7:0]
D3
D3
X
CONTRAST[6:0]
GGAIN[6:0]
BGAIN[6:0]
RGAIN[6:0]
D3
X
X
X
C2R[2:0]
C2R[2:0]
D2
D2
X
D2
X
X
X
DC OFFSET[2:0]
C1R[2:0]
C1R[2:0]
D1
D1
X
C2B[2:1]
C2B[2:1]
D1
PS
X
PFR[1:0]
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C1B[2]
C1B[2]
SRST
D0
D0
X
BV
D0