LM1276AAA National Semiconductor, LM1276AAA Datasheet - Page 33

• Manufacturer Part Number: LM1276AAA
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

Bit 5
Bit 6
Bit 7
Bits 4–0
Bits 7–5
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Control Register Definitions
Frame Control Register 2:
Character Font Access Register:
Fade In/Out Enable. When this bit is a 1, the OSD Fade In/Fade Out function is enabled. When this bit is a 0, the
function is disabled.
Auto Size Enable. When this bit is a 1, the Auto Size function is enabled. Once video detection and measurement
is completed, the bit will automatically clear itself back to 0.
Auto Size Done. When the device has completed Auto Size calculations, this bit will automatically be set high by
the chip to indicate to the MCU that the Auto Size data registers are valid and available. This bit is automatically
cleared when the MCU sets the ASZEN bit (0x8400[6]), or when the device programs a calibration sequence for
the Windows HiBrite software.
Blink Period. These five bits set the blink period of the blinking feature, which is determined by mulitiplying the
value of these bits by 8, and then multiplying the result by the vertical field rate.
Pixels per Line. These three bits determine the number of pixels per line of OSD characters. See Table 23, which
gives the maximum horizontal scan rate. Also see Table 2.
This is the Color Bit Plane Selector. This bit must be set to 0 to read or write a two-color attribute from the range
0x0000 to 0x2FFF. When reading or writing four-color attributes from the range 0x3000 to 0x3FFF, this bit is set to
0 for the least significant plane and to 1 for the most significant plane. It is also required to set this bit to read the
individual bit planes of the four color character fonts in 0x3000 to 0x3FFF and 0x7000 to 0x7FFF.
This is the Character/Attribute Selector. This applies to reads from the Display Page RAM (address range
0x8000–0x81FF). When a 0, the character code is returned and when a 1, the attribute code is returned.
This selects the V input polarity.
If bit = 0, a positive H Sync input signal is required. (Default)
If bit = 1, a negative H Sync input signal is required.
This selects the V sync input polarity.
If bit = 0, a positive V Sync input signal is required. (Default)
If bit = 1, a negative V Sync input signal is required.
This bit limits the period during which video data may be detected.
If the bit is set to 1 then the valid data active period is limited to the vertical blanking time, as set by the vertical
blanking register. If a string of 80 clock pulses is received during this time it is accepted as valid. If a string of 80
pulses is not received until during the active video time, then this data is ignored. If the bit is set to ‘0’ (default),
then the first 80 pulse clock string that is detected is considered to be valid, even if this is during the active video
time.
Bits 7–5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
RESET
SRST
Reserved Reserved
Pixels per Line
RSV
PL[2:0]
RSV
TABLE 23. OSD Pixels per Line
(Continued)
CHARFONTACC (0x8402)
FRMCTRL2 (0x8401)
1024 pixels per line
1088 pixels per line
1152 pixels per line
704 pixels per line
768 pixels per line
832 pixels per line
896 pixels per line
960 pixels per line
LIMIT
VDI
Description
33
VSYPOL
V Sync
Blink Period
BP[4:0]
HSYPOL
H Sync
Max Horizontal Frequency (kHz)
Select
ATTR
FONT4
Plane
108
102
110
110
110
110
110
96
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