DSP56156 Motorola Inc, DSP56156 Datasheet - Page 29
DSP56156
Manufacturer Part Number
DSP56156
Description
16-bit Digital Signal Processor
Manufacturer
Motorola Inc
Datasheet
1.DSP56156.pdf
(76 pages)
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External Bus Synchronous Timing
(V
Table 15 lists external bus synchronous timing. Figure 17 and illustrate the bus timings
with no wait states and two wait states, respectively.
MOTOROLA
NOTE:
CC
Num
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
= 5.0 V dc ± 10%, T
10 ns C
EXTAL CLK In High to CLKO High
CLKO High to
BS Width Deasserted
CLKO High to WR Asserted Low
WR and RD Deasserted High to BS
Asserted Low (2 Successive Bus Cycles)
<intentionally blank>
CLKO High to BS Deasserted
TA Valid to CLKO High (Setup)
CLKO High to TA Invalid (Hold)
CLKO High to D0-D15 Out Valid
CLKO High to D0-D15 Out Invalid
D0-D15 In Valid to CLKO Low (Setup)
CLKO Low to D0-D15 In Invalid (Hold)
CLKO Low to WR, RD Deasserted
WR, RD Hold Time from CLKO Low
CLKO High to D0-D15 Three-state
CLKO High to D0-D15 Out Active
CLKO High to A0-A15, PS/DS, R/W Invalid
a. A0-A15 Valid
b. PS/DS, R/W Valid, BS, RD Asserted
L
= 25 pF
Freescale Semiconductor, Inc.
Characteristic
For More Information On This Product,
J
= -40 to +125 C, C
Table 15 External Bus Synchronous Timing
Go to: www.freescale.com
DSP56156 Data Sheet
L
= 50 pF + 1 TTL Load)
T+3.1
Min
18.3
14.3
4.7
4.7
2.6
4.5
1.7
2.0
2.2
2.8
2.4
1.2
—
0
6
0
0
40 MHz
T+12.4
Max
15.8
10.3
7.1
4.2
12
14
—
—
—
—
—
—
10
—
—
9
6
T+3.1
Min
13.4
11.8
2.6
4.5
1.7
2.0
2.4
4.7
4.7
2.2
1.2
2.8
—
AC Electrical Characteristics and Timing
0
6
0
0
50 MHz
T+12.4
Max
13.3
10.3
7.1
4.2
12
14
10
External Bus Synchronous Timing
—
—
—
—
—
—
—
—
9
6
T+3.1
10.2
Min
2.0
2.4
4.7
4.7
9.8
2.6
4.5
1.7
2.2
1.2
2.8
—
0
6
0
0
60 MHz
(See Note)
T+12.4
Max
11.8
10.3
7.1
4.2
12
—
10
—
—
—
—
—
—
—
9
4
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29
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