DSP56364D Motorola Inc, DSP56364D Datasheet - Page 49

• Manufacturer Part Number: DSP56364D
• Description: 24-Bit Audio Digital Signal Processor
• Manufacturer: Motorola Inc

Notes:
MOTOROLA
No.
149
150
151
152
153
154
155
156
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
WR assertion to CAS assertion
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
5.
6.
Table 2-12 DRAM Page Mode Timings, Four Wait States
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g.,
t
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each
DRAM out-of-page access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
t
PC
GZ
.
equals 3
Characteristics
T
C
Freescale Semiconductor, Inc.
for read-after-read or write-after-write sequences).
For More Information On This Product,
DSP56364 Advance Information
6
Go to: www.freescale.com
Symbol
External Memory Expansion Port (Port A)
t
t
WCS
ROH
t
t
t
t
DH
GA
DS
GZ
1.25
3.25
0.75
0.5
3.5
4.5
Expression
0.25
DSP56364
T
T
T
T
T
T
C
C
C
1, 2, 3
C
C
C
T
C
4.0
4.0
4.0
4.3
7.0
0.3
(continued)
.
31.0
41.0
Min
1.0
8.2
0.0
7.2
—
—
Specifications
OFF
Max
25.5
2.5
—
—
—
—
—
—
and not
Unit
2-29
ns
ns
ns
ns
ns
ns
ns
ns