DSP56364D Motorola Inc, DSP56364D Datasheet - Page 68
DSP56364D
Manufacturer Part Number
DSP56364D
Description
24-Bit Audio Digital Signal Processor
Manufacturer
Motorola Inc
Datasheet
1.DSP56364D.pdf
(162 pages)
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Note: Periodically sampled, not 100% tested
153
154
157
158
159
160
162
163
Specifications
Serial Host Interface SPI Protocol Timing
No.
161
2-48
SCK edge to data out not valid
(data out hold time)
SS assertion to data out valid
(CPHA = 0)
First SCK sampling edge to HREQ
output deassertion
Last SCK sampling edge to HREQ
output not deasserted (CPHA = 1)
SS deassertion to HREQ output not
deasserted (CPHA = 0)
SS deassertion pulse width (CPHA =
0)
HREQ in assertion to first SCK edge
HREQ in deassertion to last SCK
sampling edge (HREQ in set-up time)
(CPHA = 1)
First SCK edge to HREQ in not
asserted
(HREQ in hold time)
Table 2-17 Serial Host Interface SPI Protocol Timing (continued)
Characteristics
Freescale Semiconductor, Inc.
For More Information On This Product,
DSP56364 Advance Information
Go to: www.freescale.com
Master/
Master Bypassed
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Bypassed
Bypassed
Bypassed
Narrow
Narrow
Narrow
Narrow
Mode
Filter
Wide
Wide
Wide
Wide
—
—
—
—
—
0.5
0.5 t
0.5 t
2.5 T
2.5 T
2.5 T
Expression
2.5 T
2.5 T
2.5 T
2.5 T
2.5 T
2.5 T
2.5 T
T
T
T
T
T
C
C
C
C
+106
C
t
SPICC
SPICC
+55
+33
SPICC
0
0
C
C
C
+5
+6
C
C
C
C
C
C
C
+120
+217
+136
+30
+30
+80
+30
+43
+43
+43
+
+
+
Min
116
105
161
121
174
209
15
65
55
55
16
—
—
—
—
0
0
MOTOROLA
Max
145
242
—
—
—
43
55
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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