DSP56F803 Motorola Inc, DSP56F803 Datasheet - Page 10

• Manufacturer Part Number: DSP56F803
• Description: 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

2.5 Interrupt and Program Control Signals
10
No. of
No. of
Pins
Pins
1
1
1
1
1
1
Signal
Name
WR
PS
DS
RD
Signal
Name
IRQA
IRQB
Signal
Output
Output
Output
Output
Type
Table 10. Interrupt and Program Control Signals
(Schmitt)
(Schmitt)
Signal
Type
Input
Input
Freescale Semiconductor, Inc.
State During
Tri-stated
Tri-stated
Tri-stated
Tri-stated
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Reset
Table 9. Bus Control Signals
State During
Reset
Input
Input
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Program Memory Select—PS is asserted low for external Program
memory access.
Data Memory Select—DS is asserted low for external Data memory
access.
Write Enable—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the
device puts data on the bus. When WR is deasserted high, the
external data is latched inside the external device. When WR is
asserted, it qualifies the A0–A15, PS, and DS pins. WR can be
connected directly to the WE pin of a Static RAM.
Read Enable—RD is asserted during external memory read cycles.
When RD is asserted low, pins D0–D15 become inputs and an
external device is enabled onto the device data bus. When RD is
deasserted high, the external data is latched inside the hybrid
controller. When RD is asserted, it qualifies the A0–A15, PS, and DS
pins. RD can be connected directly to the OE pin of a Static RAM or
ROM.
External Interrupt Request A—The IRQA input is a
synchronized external interrupt request indicating an
external device is requesting service. It can be programmed
to be level-sensitive or negative-edge- triggered.
External Interrupt Request B—The IRQB input is an
external interrupt request indicating an external device is
requesting service. It can be programmed to be level-
sensitive or negative-edge-triggered.
Signal Description
Signal Description
56F803 Technical Data