DSP56F803 Motorola Inc, DSP56F803 Datasheet - Page 27

• Manufacturer Part Number: DSP56F803
• Description: 16-bit Hybrid Controller
• Manufacturer: Motorola Inc

Operating Conditions:
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F803 Technical Data
RESET Assertion to Address, Data and Control
Signals High Impedance
Minimum RESET Assertion Duration
OMR Bit 6 = 0
OMR Bit 6 = 1
RESET De-assertion to First External Address Output
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
IRQA Width Assertion to Recover from Stop State
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
(See Note)
A0–A15,
D0–D15
PS, DS
WR
RD
Table 29. Reset, Stop, Wait, Mode Select, and Interrupt Timing
Characteristic
t
AWR
t
V
WRWR
3
Figure 13. External Bus Asynchronous Timing
t
SS
WRD
= V
Freescale Semiconductor, Inc.
SSA
For More Information On This Product,
= 0 V, V
t
DOS
2
t
WR
DD
Go to: www.freescale.com
= V
Data Out
DDA
4
t
ARDA
= 3.0–3.6V, T
t
WRRD
Symbol
t
t
t
t
Reset, Stop, Wait, Mode Select, and Interrupt Timing
RAZ
t
RDA
t
IRW
IDM
t
t
RA
IRI
IW
IG
t
DOH
A
t
AD
= –40 to +85 C, C
275,000T
t
ARDD
128T
1.5T
Min
33T
15T
16T
13T
t
2T
—
RD
Data In
t
RDD
L
Max
34T
21
—
—
—
—
—
—
—
t
t
50pF
RDRD
RDWR
t
t
DRD
Unit
RDA
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 5
Figure 14
Figure 14
Figure 14
Figure 15
Figure 16
Figure 16
Figure 17
Figure 18
Figure
See
27