M30302MEP-xxx Renesas Technology, M30302MEP-xxx Datasheet - Page 12

• Manufacturer Part Number: M30302MEP-xxx
• Description: (M30302Mx) Single-Chip 16-Bit CMOS Microcomputer
• Manufacturer: Renesas Technology

Under development
M16C/30P Group
Rev.0.80
REJ03B0088-0080
3.
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1M bytes from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte
internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses
from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no
functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
Figure 3.1
Memory
5 kbytes
6 kbytes
Size
Internal RAM
Mar 18, 2005
Address XXXXXh
Preliminary specification
Specifications in this manual are tentative and subject to change.
Memory Map
01BFFh
017FFh
Page 12 of 34
128 kbytes
192 kbytes
96 kbytes
Size
Internal ROM
Address YYYYYh
D0000h
E8000h
E0000h
XXXXXh
YYYYYh
FFFFFh
00000h
00400h
Reserved area
Internal ROM
Internal RAM
SFR
FFFDCh
FFFFFh
FFE00h
Undefined instruction
Watchdog timer
BRK instruction
Address match
Special page
vector table
Single step
Overflow
Reset
DBC
NMI
3. Memory