LM3489QMM National Semiconductor, LM3489QMM Datasheet - Page 10

• Manufacturer Part Number: LM3489QMM
• Description: LM3489/LM3489Q Hysteretic PFET Buck Controller with Enable Pin; Package: MINI SOIC; No of Pins: 8; Qty per Container: 1000; Container: Reel
• Manufacturer: National Semiconductor

www.national.com
At high input voltages (>28V) increased undershoot at the
switch node can cause an increase in the current limit thresh-
old. To avoid this problem, a low Vf Schottky catch diode must
be used (See Catch Diode Selection). Additionally, a resistor
can be placed between the ISENSE pin and the switch node.
Any value in the range of 220Ω to 600Ω is recommended.
START UP
The current limit circuit is active during start-up. During start-
up the PFET will stay on until either the current limit or the
feedback comparator is tripped
If the current limit comparator is tripped first then the fold back
characteristic should be taken into account. Start-up into full
load may require a higher current limit set point or the load
must be applied after start-up.
One problem with selecting a higher current limit is inrush
current during start-up. Increasing the capacitance (C
parallel with R
and R
activate at a lower current. The output voltage will ramp more
slowly when using this technique. There is example start-up
plot for C
acteristics. Lower values for C
on soft-start.
EXTERNAL SENSE RESISTOR
The V
ature. This will result an equivalent variation in current limit.
To improve current limit accuracy an external sense resistor
can be connected from V
shown in Figure 5. The current sense resistor, R
have value comparable with R
cally in the range of 50mΩ to 200 mΩ. The equation in the
Current Limit Operation section can be used by replacing the
R
DSON
FIGURE 4. Current Limit Fold Back Phenomenon
DS
ADJ
with R
of a PFET will tend to vary significantly over temper-
ADJ
create an RC time constant forcing current limit to
equal to 1nF in the Typical Performance Char-
CS
ADJ
.
results in a soft-start characteristic. C
IN
to the source of the PFET, as
ADJ
DSON
will have little to no effect
of the PFET used, typi-
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CS
should
ADJ
) in
ADJ
10
PGATE
When switching, the PGATE pin swings from VIN (off) to
some voltage below VIN (on). How far the PGATE will swing
depends on several factors including the capacitance, on
time, and input voltage.
PGATE voltage swing will increase with decreasing gate ca-
pacitance. Although PGATE voltage will typically be around
VIN-5V, with very small gate capacitances, this value can in-
crease to a typical maximum of VIN-8.3V.
Additionally, PGATE swing voltage will increase as on time
increases. During long on times, such as when operating at
100% duty cycle, the PGATE voltage will eventually fall to its
maximum voltage of VIN-8.3V (typical) regardless of the
PFET gate capacitance.
The PGATE voltage will not fall below 0.4V (typical). There-
fore, when the input voltage falls below approximately 9V, the
PGATE swing voltage range will be reduced. At an input volt-
age of 7V, for instance, PGATE will swing from 7V to a
minimum of 0.4V.
DEVICE ENABLE, SHUTDOWN
The LM3489 can be remotely shutdown by forcing the enable
pin to ground. With EN pin grounded, the internal blocks other
than the enable logic are de-activated and the shutdown cur-
rent of the device will be lowered to only 7µA (typical). Re-
leasing the EN pin allows for normal operation to resume. The
EN pin is internally pulled high with the voltage clamped at 8V
typical. For normal operation this pin should be left open. In
case an external voltage source is applied to this pin for en-
able control, the applied voltage should not exceed the max-
imum operating voltage level specified in this datasheet, i.e.
5.5V.
ADJUSTABLE UVLO
The under-voltage-lockout function can be implemented as
shown in Figure 6. By incorporating the feature of the internal
enable threshold, the lockout level can be programmed
through an external potential divider formed with R3 and R4.
The input voltage information is detected and compared with
the enable threshold and the device operation will be inhibited
when V
hysteresis voltage can be calculated as follows:
FIGURE 5. Current Sensing by External Resistor
IN
drops below the preset UVLO level. The UVLO and
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