LM3489QMM National Semiconductor, LM3489QMM Datasheet - Page 9

• Manufacturer Part Number: LM3489QMM
• Description: LM3489/LM3489Q Hysteretic PFET Buck Controller with Enable Pin; Package: MINI SOIC; No of Pins: 8; Qty per Container: 1000; Container: Reel
• Manufacturer: National Semiconductor

For example, with V
Operating frequency (F) is determined by knowing the input
voltage, output voltage, inductor, V
ries Resistance) of output capacitor, and the delay. It can be
approximately calculated using the formula:
where:
α: (R1 + R2) / R2
the PFET delay time. The propagation delay is 90ns
cally. (See the Propagation Delay curve below.)
The operating frequency and output ripple voltage can also
be significantly influenced by the speed up capacitor (Cff). Cff
is connected in parallel with the high side feedback resistor,
R1. The location of this capacitor is similar to where a phase
lead capacitor would be located in a PWM control scheme.
However it's effect on hysteretic operation is much different.
Cff effectively shorts out R1 at the switching frequency and
applies the full output ripple to the FB pin without dividing by
the R2/R1 ratio. The end result is a reduction in output ripple
and an increase in operating frequency. When adding Cff,
calculate the formula above with α = 1. The value of Cff de-
pend on the desired operating frequency and the value of R2.
A good starting point is 470pF ceramic at 100kHz decreasing
linearly with increased operating frequency. Also note that as
the output voltage is programmed below 2.5V, the effect of
Cff will decrease significantly.
CURRENT LIMIT OPERATION
The LM3489 has a cycle-by-cycle current limit. Current limit
is sensed across the V
sense resistor. When current limit is activated, the LM3489
turns off the external PFET for a period of 9µs(typical). The
current limit is adjusted by an external resistor, R
The current limit circuit is composed of the ISENSE compara-
tor and the one-shot pulse generator. The positive input of the
ISENSE comparator is the ADJ pin. An internal 5.5µA current
delay: It includes the LM3489 propagation delay time and
V
OUT_PP
V
FIGURE 2. Propagation Delay
OUT_PP
= 0.01 x (33K + 20k) / 20k = 0.0266V
OUT
DS
= V
set to 3.3V, V
of the PFET or across an additional
HYST
(R1 + R2) / R2
HYST
OUT_PP
, ESR (Equivalent Se-
is 26.6mV
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ADJ
.
typi-
9
sink creates a voltage across the external R
voltage is compared to the voltage across the PFET or sense
resistor. The ADJ voltage can be calculated as follows:
Where 3.0µA is the minimum I
The negative input of the ISENSE comparator is the ISENSE
pin that should be connected to the drain of the external
PFET. The inductor current is determined by sensing the
V
The current limit is activated when the voltage at the ADJ pin
exceeds the voltage at the I
tor triggers the 9µs one shot pulse generator forcing the driver
to turn the PFET off. The driver turns the PFET back on after
9µs. If the current has not reduced below the set threshold,
the cycle will repeat continuously.
A filter capacitor, C
3. C
will not be accidentally triggered. A value of 100pF to 1nF is
recommended in most applications. Higher values can be
used to create a soft-start function (See Start Up section).
The current limit comparator has approximately 100ns of
blanking time. This ensures that the PFET is fully on when the
current is sensed. However, under extreme conditions such
as cold temperature, some PFETs may not fully turn on within
the blanking time. In this case, the current limit threshold must
be increased. If the current limit function is used, the on time
must be greater than 100ns. Under low duty cycle operation,
the maximum operating frequency will be limited by this min-
imum on time.
During current limit operation, the output voltage will drop sig-
nificantly as will operating frequency. As the load current is
reduced, the output will return to the programmed voltage.
However, there is a current limit fold back phenomenon in-
herent in this current limit architecture. See Figure 4.
DS
. It can be calculated as follows.
ADJ
V
filters unwanted noise so that the ISENSE comparator
ISENSE
FIGURE 3. Current Sensing by V
= V
V
ADJ
IN
ADJ
− (R
= V
, should be placed as shown in Figure
DSON
IN
SENSE
− (R
x I
CL-ADJ
ADJ
IND_PEAK
pin. The ISENSE compara-
x 3.0µA)
value.
) = V
ADJ
IN
DS
resistor. This
− V
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20186925
DS