LM3489QMM National Semiconductor, LM3489QMM Datasheet - Page 12

• Manufacturer Part Number: LM3489QMM
• Description: LM3489/LM3489Q Hysteretic PFET Buck Controller with Enable Pin; Package: MINI SOIC; No of Pins: 8; Qty per Container: 1000; Container: Reel
• Manufacturer: National Semiconductor

www.national.com
The input capacitor power dissipation can be calculated as
follows.
The input capacitor must be able to handle the RMS current
and the dissipation. Several input capacitors may be con-
nected in parallel to handle large RMS currents. In some
cases it may be much cheaper to use multiple electrolytic ca-
pacitors than a single low ESR, high performance capacitor
such as OS-CON or Tantalum. The capacitance value should
be selected such that the ripple voltage created by the switch
current pulses is less than 10% of the total DC voltage across
the capacitor.
For high VIN conditions (> 28V), the fast switching, high swing
of the internal gate drive introduces unwanted disturbance to
the VIN rail and the current limit function can be affected. In
order to eliminate this potential problem, a high quality ce-
ramic capacitor of 0.1 µF is recommended to filter out the
internal disturbance at the VIN pin. This capacitor should be
placed right next to the VIN pin for best performance.
PROGRAMMING THE CURRENT LIMIT (R
The current limit is determined by connecting a resistor
(R
where:
Using the minimum value for I
current limit threshold will be set higher than the peak inductor
current.
The R
at the ADJ pin does not fall below 3.5V. With this in mind,
R
set the desired current limit, either use a PFET with a lower
R
The current limit function can be disabled by connecting the
ADJ pin to ground and ISENSE to VIN.
CATCH DIODE SELECTION (D1)
The important parameters for the catch diode are the peak
current, the peak reverse voltage, and the average power
dissipation. The average current through the diode can be
calculated as following.
The off state voltage across the catch diode is approximately
equal to the input voltage. The peak reverse voltage rating
must be greater than input voltage. In nearly all cases a
Schottky diode is recommended. In low output voltage appli-
cations a low forward voltage provides improved efficiency.
For high temperature applications, diode leakage current may
become significant and require a higher reverse voltage rating
to achieve acceptable performance.
P-CHANNEL MOSFET SELECTION (Q1)
The important parameters for the PFET are the maximum
Drain-Source voltage (V
rent rating, and the input capacitance.
ADJ_MAX
DSON
R
I
I
ADJ
CL_ADJ
IND_PEAK
DSON
) between input voltage and the ADJ pin, pin 5.
ADJ
, or use a current sense resistor as shown in Figure 5.
: Drain-Source ON resistance of the external PFET
: 3.0µA minimum
= (V
value must be selected to ensure that the voltage
= I
IN
LOAD
-3.5)/7µA. If a larger R
P
D(CIN)
+ I
I
D_AVE
RIPPLE
= I
DS
= I
RMS_CIN
), the on resistance (R
/2
OUT
CL_ADJ
x (1 − D)
2
x ESR
(3.0µA) ensures that the
ADJ
CIN
value is needed to
ADJ
)
DSON
), Cur-
12
The voltage across the PFET when it is turned off is equal to
the sum of the input voltage and the diode forward voltage.
The V
input voltage.
PFET drain current, Id, must be rated higher than the peak
inductor current, I
Depending on operating conditions, the PGATE voltage may
fall as low as V
with a V
PGATE swing voltage.
As input voltage desreases below 9V, PGATE swing voltage
may also decrease. At 5.0V input the PGATE will swing from
V
and completely, a low threshold PFET should be used when
the input voltage is less than 7V.
Total power loss in the FET can be approximated using the
following equation:
where:
A PFET should be selected with a turn on rise time of less
than 100ns. Slower rise times will degrade efficiency, can
cause false current limiting, and in extreme cases may cause
abnormal spiking at the PGATE pin.
The R
value, R
coefficient. At 100°C, the R
higher than the 25°C value. This increase in R
considered when determining R
applications. If the current limit is set based upon 25°C rat-
ings, then false current limiting can occur at high temperature.
Keeping the gate capacitance below 2000pF is recommend-
ed to keep switching losses and transition times low. This will
also help keep the PFET drive current low, which will improve
efficiency and lower the power dissipation within the con-
troller.
As gate capacitance increases, operating frequency should
be reduced and as gate capacitance decreases operating
frequency can be increased.
INTERFACING WITH THE ENABLE PIN
The enable pin is internally pulled high with clamping at 8V
typical. For normal operation this pin should be left open. To
disable the device, the enable pin should be connected to
ground externally. If an external voltage source is applied to
this pin for enable control, the applied voltage should not ex-
ceed the maximum operating voltage level specified in this
datasheet, i.e. 5.5V. For most applications, an open drain or
open collector transistor can be used to short this pin to
ground to shutdown the device .
IN
PD
t
t
A value of 10ns to 20ns is typical for ton and toff.
on
off
to V
switch
= FET turn on time
= FET turn off time
DS
DSON
IN
ADJ
must be selected to provide some margin beyond the
GS
= R
- 4.6V. To ensure that the PFET turns on quickly
. Note that the R
is used in determining the current limit resistor
maximum rating greater than the maximum
DSON
IN
- 8.3V. Therefore, a PFET must be selected
IND-PEAK
x I
OUT
2
.
x D + F x I
DSON
DSON
ADJ
has a positive temperature
may be as much as 150%
in wide temperature range
OUT
x V
IN
x (t
DSON
on
+ t
must be
off
)/2